代码搜索结果

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Led is port (En:in std_logic; Numin: in integer range 0 to 9; Numout: out std_logic_vector(0 to 6) ); en

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PS2 is port ( KBdata: in STD_LOGIC; KBCLK: in STD_LOGIC; DOUT: out STD_LOGIC_VEC

--Generated Binary Up Counter --The first design entity is a T-type flip-flop. The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce regular

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY vote7 IS PORT ( men : IN std_logic_vector(6 downto 0); pass,stop : buffer std_logic ); END vote7; ARCHITECTU

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT8 IS PORT ( CLK, LD : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CAO

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity pluse is port (data : in std_logic_vector(7 downto 0); start,clk : in std

--8-bit Register with Synchronous Load and Clear The design entity shows the standard way of describing a register using a synchronous process, ie. a process containing a single wait statement which i

library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity caideng is port(clk ,clr:in std_logic; dout:out std_logic_vector(7 downto 0)); end; architecture bhv of c

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity cnt20 is port (stop,start,reset,clk:in std_logic; q:out std_logic_vector(7 downto 0);