led.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Led is
port
(En:in std_logic;
 Numin: in integer range 0 to 9;
 Numout: out std_logic_vector(0 to 6)
);
end;

architecture a of Led is
begin 
 process(En,Numin)
  begin
    if En='1' then
      case Numin is
         when 0=>Numout<="1111110";
         when 1=>Numout<="0110000";
         when 2=>Numout<="1101101";
         when 3=>Numout<="1111001";
         when 4=>Numout<="0110011";
         when 5=>Numout<="1011011";
         when 6=>Numout<="0011111";
         when 7=>Numout<="1110000";
         when 8=>Numout<="1111111";
         when 9=>Numout<="1110011";
         when others=>Numout<="0000000";
      end case;
     else
           Numout<="0000000";
     end if;
    end process;
   end a;