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Logic Analyzer 的代码
lab3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab3 is
port( S2S1S0 : IN std_logic_vector(2 downto 0);
A1 :in std_logic_vector(3 downto 0);
B1
dfgadg.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab3 is
port( S2S1S0 : IN std_logic_vector(2 downto 0);
A1 :in std_logic_vector(3 downto 0);
B1
ex_p4_28_bcd_add.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCD_ADDER is
port (A,B:in std_logic_VECTOR(3 downto 0);
S: out std_logic_VECTOR(3 downto 0);
Cin : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity empty_flag_reg is
generic(
addr_width : integer := 6;
c_enable_rlocs : integer := 0
);
port(
rst
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity full_flag_reg is
generic(
addr_width : integer := 6;
c_enable_rlocs : integer := 0
);
port(
rst
sine.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine is
port(
clk:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
end entity sine;
architecture
encdec_8b10b_tb.vhd
-------------------------------------------------------------------------------
--
-- Title : Test Bench for enc_8b10b and dec_8b10b
-- Design : 8b-10b Encoder/Decoder Test Bench
-- Project : 8000
enc_8b10b_tb.vhd
-------------------------------------------------------------------------------
--
-- Title : Test Bench for enc_8b10b
-- Design : 8b/10b Encoder Test Bench
-- Project : 8000 - 8b10b_encdec
-- Au
pre_norm_fmul_arch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_misc.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY pre_norm_fmul IS
PORT(
clk : IN std_logic ;
fpu_op : IN
tabletennis.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY tabletennis IS
PORT(clk,p1,p2,reset,speed_sel,first_sel,judge: IN STD_LOGIC;
led: OUT STD_LOGIC_