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Logic Analyzer 的代码
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
result_mux.vhd
-- SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: result_mux.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
--------------------------------------
cordic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity CORDIC_ELEMENT is
generic(N:integer:=12;--No of bits in register
SHIFT:integer:=0);--Shift count for this stage
p
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
key_tbw.vhw
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
key_tbw.timesim_vhw
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
keydecoder.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY keydecoder_deb IS
PORT(
keyin :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
keydrv :IN STD_LOGIC_VECTOR(3 DOW
butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
bin_add_4bit.vhd
--************************************
--* 4 Bit Binary Full Adder *
--* Filename : BIN_ADD_4BIT.VHD *
--************************************
library IEEE;
use IEEE.STD_LOGIC_1164