result_mux.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-- SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: result_mux.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Result_Mux - entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        result_mux.vhd
-- Version:         v1.00a
-- Description:     Implements the result mux which selects the right result
--                  for writing into the register file
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              result_mux.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Result_Mux is

  generic (
    C_DATA_SIZE : natural range 4 to 64 := 32;
    C_TARGET    : TARGET_FAMILY_TYPE
    );
  port (
    Clk                : in  std_logic;
    Reset              : in  boolean;
    Result_Sel         : in  std_logic_vector(0 to 1);
    Doublet_Read       : in  boolean;
    Quadlet_Read       : in  boolean;
    -- Hexlet_Read        : in  boolean;
    Sext8              : in  boolean;
    Sext16             : in  boolean;
    -- Sext32             : in  boolean;
    PCMP_Instr         : in  boolean;
    Op1                : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Mul_Result         : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Other_Result       : in  std_logic_vector(0 to C_DATA_SIZE-1);
    ALU_Result         : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Shift_Logic_Result : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Data_Read          : in  std_logic_vector(0 to C_DATA_SIZE-1);
    EX_Result          : out std_logic_vector(0 to C_DATA_SIZE-1);
    New_Reg_Value      : out std_logic_vector(0 to C_DATA_SIZE-1)
    );

end entity Result_Mux;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Result_Mux is

  component Result_Mux_Bit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Clk   : in std_logic;
      -- Reset : in boolean;

      Result_Sel         : in  std_logic_vector(0 to 1);
      Mul_Result         : in  std_logic;
      Other_Result       : in  std_logic;
      ALU_Result         : in  std_logic;
      Shift_Logic_Result : in  std_logic;
      Data_Read          : in  std_logic;
      Data_Read_Mask     : in  std_logic;
      EX_Result          : out std_logic;
      New_Reg_Value      : out std_logic
      );
  end component Result_Mux_Bit;

  signal data_Read_Mask : std_logic_vector(0 to C_DATA_SIZE-1);

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- IMP

  data_Read_Mask(C_DATA_SIZE-8 to C_DATA_SIZE-1) <= "11111111";  -- Always enabled the lowest
                                                                      -- byte
  DATA_SIZE_gt_8 : if C_DATA_SIZE > 8 generate

    Mask_LSB_1 : process (Doublet_Read, Op1, Sext8, PCMP_Instr) is
      variable Upper_Byte_Mask : std_logic_vector(0 to 7);
    begin  -- process Mask_LSB_1
      Upper_Byte_Mask :=  (others => Op1(C_DATA_SIZE-8));
      if Sext8 then
        data_Read_Mask(C_DATA_SIZE-16 to C_DATA_SIZE-9) <= Upper_Byte_Mask;
      elsif Doublet_Read and not PCMP_Instr then
        data_Read_Mask(C_DATA_SIZE-16 to C_DATA_SIZE-9) <= "11111111";
      else                              -- Byte Read
        data_Read_Mask(C_DATA_SIZE-16 to C_DATA_SIZE-9) <= "00000000";
      end if;
    end process Mask_LSB_1;

    DATA_SIZE_gt_16 : if C_DATA_SIZE > 16 generate

      Mask_DOUBLET_MSB : process (Sext8, Sext16, Op1, Quadlet_Read, PCMP_Instr) is
        variable Upper_extend : std_logic_vector(0 to 15);
      begin  -- process Mask_DOUBLET_MSB
        if Sext8 then
          Upper_extend := (others => Op1(C_DATA_SIZE-8));
        elsif Sext16 then
          Upper_extend := (others => Op1(C_DATA_SIZE-16));
        elsif Quadlet_Read and not PCMP_Instr then
          Upper_extend := "1111111111111111";
        else                            -- Byte or Doublet Read
          Upper_extend := "0000000000000000";
        end if;
        data_Read_Mask(C_DATA_SIZE-32 to C_DATA_SIZE-17) <= Upper_extend;
      end process Mask_DOUBLET_MSB;

    end generate DATA_SIZE_gt_16;

  end generate DATA_SIZE_gt_8;

  Using_FPGA : if (C_TARGET /= RTL) generate
    
    Result_Mux_Bits : for I in C_DATA_SIZE-1 downto 0 generate
      Result_Mux_Bit_I : Result_Mux_Bit
        generic map (
          C_TARGET => C_TARGET)
        port map (
          Clk                => Clk,                    -- [in]
          -- Reset              => Reset,                  -- [in]
          Result_Sel         => Result_Sel,             -- [in]
          Mul_Result         => Mul_Result(I),          -- [in]
          Other_Result       => Other_Result(I),        -- [in]
          ALU_Result         => ALU_Result(I),          -- [in]
          Shift_Logic_Result => Shift_Logic_Result(I),  -- [in]
          Data_Read          => Data_Read(I),           -- [in]
          Data_Read_Mask     => data_Read_Mask(I),      -- [in]
          EX_Result          => EX_Result(I),           -- [out]
          New_Reg_Value      => New_Reg_Value(I));      -- [out]
    end generate Result_Mux_Bits;
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate
    signal ex_Result_i : std_logic_vector(EX_Result'range);
  begin
    Result_Sel_Process: process (Result_Sel, Mul_Result, Other_Result,
                                 ALU_Result, Shift_Logic_Result, Data_Read,
                                 Data_Read_Mask) is
    begin  -- process Result_Sel_Process
      case Result_Sel is
        when "00" => ex_Result_i <= ALU_Result;
        when "01" => ex_Result_i <= Other_Result or Mul_Result;
        when "10" => ex_Result_i <= Data_Read_Mask and Shift_Logic_Result;
        when "11" => ex_Result_i <= Data_Read_Mask and Data_Read;
        when others => null;
      end case;
    end process Result_Sel_Process;

    Ex_Result_DFF: process (Clk) is
    begin  -- process Ex_Result_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        New_Reg_Value <= ex_Result_i;
      end if;
    end process Ex_Result_DFF;

    EX_Result <= ex_Result_i;
    
  end generate Using_RTL;

end architecture IMP;