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Logic Analyzer 的代码
iface.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS
ctl_1.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_1 is
Port(
wr :in std_logic; -- 作时钟使用
A :in std_logic_vector(15 downto 0); -- 16位地址线
D :in std_logic_vector(7 downto 0); --
ctl_2.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_2 is
Port(
clk :in std_logic; -- 作时钟使用
P1_0 :in std_logic; -- 控制脉冲宽度
T :in std_logic_vector(19 downto 0); -- 20位中间控制信号
Q :
display1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--调时和调价输出的切换
entity display1 is
port(
flag1 :in std_logic; --调价标志
flag2 :in std_logic;
displayswitch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity displayswitch is
port
( switch : in std_logic;
up : in std_logic_vector(3 downto 0);
pri
shezhi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shezhi is
port
( mode : in std_logic;
sure : in std_logic;
up : in std_logic
multi8x8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity multi8x8 is port(
clk : in std_logic;
start : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 dow
etester.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ETESTER IS
PORT(BCLK,TCLK,CLR,CL,SPUL : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
START,EEND :
contral.vhd
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY contrOl IS
PORT
(
clk : IN STD_LOGI