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Logic Analyzer 的代码
data_core.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLKK : IN STD_LOGIC;
FWORD
reg.vhd
-- reg.vhd
-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. T
pc.vhd
-- pc.vhd
-- This module implements the 16-bit program Counter (PC). PC is loaded from
-- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to
-- zero when "reset" is assert
topglobal.vhd
-- Top global: Nivel superior, encargado de la comunicacion entre
-- los dos subtops y de controlar los accesos de lectura y escritura
library IEEE;
use IEEE.std_logic_1164.all;
entity Topglobal
toptrata.vhd
--Toptrata: Subtop encargado de realizar el procesamiento ordenado desde Topcom
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity to
topglobal.bak
-- Top global: Nivel superior, encargado de la comunicacion entre
-- los dos subtops y de controlar los accesos de lectura y escritura
library IEEE;
use IEEE.std_logic_1164.all;
entity Topglobal
topcom.vhd
--BLOQUE TOP DE LA COMUNICACI覰
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity topcom is
port (
P16: in STD_LOGIC
scan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan is
port(clk:in std_logic;
arst:in std_logic;
outscan:out std_logic_vector(2 downto 0)
);
end scan;
clock24coms.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE clock24coms IS
COMPONENT jsq60
PORT(clk:IN STD_LOGIC;
en0,en1,cin:IN STD_LOGIC;
datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);