topglobal.vhd

Image_Filter_An_Image_halftone is performed over data loaded into the on board RAM and presented on

-- Top global: Nivel superior, encargado de la comunicacion entre
-- los dos subtops y de controlar los accesos de lectura y escritura
library IEEE;
use IEEE.std_logic_1164.all;

entity Topglobal is
    port (
        clk: in STD_LOGIC;
        busdato: inout STD_LOGIC_VECTOR (7 downto 0);
        				-- Bus de datos de la RAM
        p16: in STD_LOGIC;		
        p44: in STD_LOGIC;
        p45: in STD_LOGIC;
        p46: in STD_LOGIC;
        p47: in STD_LOGIC;
        p48: in STD_LOGIC;
        p49: in STD_LOGIC;
        eread: out STD_LOGIC;		-- Read enable
        ewrite: out STD_LOGIC;		-- Write enable
        p66: out STD_LOGIC;
        p69: out STD_LOGIC;
        p70: out STD_LOGIC;
        p77: out STD_LOGIC;
        busdirec: out STD_LOGIC_VECTOR (14 downto 0);
        				-- bus de direcciones de la RAM
        p18: out STD_LOGIC;		-- Pines para el led 7 segmentos
        p19: out STD_LOGIC;
        p20: out STD_LOGIC;
        p23: out STD_LOGIC;
        p24: out STD_LOGIC;
        p25: out STD_LOGIC;
        p26: out STD_LOGIC;
        cs: out STD_LOGIC
    );
end Topglobal;

architecture Topglobal_arch of Topglobal is

component toptrata is	-- Para el procesamiento de la imagen almacenada
port(
	clk: in STD_LOGIC;
	Rstglobal:in STD_LOGIC;
	finproc:out STD_LOGIC;
	Tammasc: in STD_LOGIC_VECTOR(1 downto 0);
	inproces: out std_logic;
	exproces:out std_logic;
	leeproc:out std_logic;
	escriproc:out std_logic;
        P19: out STD_LOGIC;  
	P18: out STD_LOGIC;
	P23: out STD_LOGIC;
	P20: out STD_LOGIC;
	P24: out STD_LOGIC;
	P26: out STD_LOGIC;
	P25: out STD_LOGIC;
	dirorig: out STD_LOGIC_VECTOR (14 downto 0);
	dirpro: out STD_LOGIC_VECTOR (15 downto 0);
        datobien: inout STD_LOGIC_VECTOR (7 downto 0);
        espeorden: in STD_LOGIC;
        pixdat: out STD_LOGIC_VECTOR (7 downto 0);
        coge:out STD_LOGIC;
        zcontrol:out STD_LOGIC;
-- Los siguientes puertos fueron usados para la simulacion,
-- pero no son necesarios en el Topglobal
	recorre:out STD_LOGIC; 
	calcmed:out STD_LOGIC;
	clasmasc: out STD_LOGIC_VECTOR (2 downto 0);
	masqui:out STD_LOGIC  
	
	);
end component;
	
component topcom is	-- Para la carga y lectura de la imagen
			-- desde el exterior
port(
	P16: in STD_LOGIC;
	P44: in STD_LOGIC;
	P45: in STD_LOGIC;
	P46: in STD_LOGIC;
	P47: in STD_LOGIC;
	P48: in STD_LOGIC;
	P49: in STD_LOGIC;
	P70: out STD_LOGIC;
	P77: out STD_LOGIC;
	P66: out STD_LOGIC;
	P69: out STD_LOGIC;
     	fproc: in STD_LOGIC;
      	clk: in STD_LOGIC;
      	dirram: out STD_LOGIC_VECTOR (14 downto 0);
      	datoraml: in STD_LOGIC_VECTOR (7 downto 0);
      	datorame: out STD_LOGIC_VECTOR (7 downto 0);
      	GReset: out STD_LOGIC;
      	flec: out STD_LOGIC;
      	tipo: out STD_LOGIC_VECTOR (1 downto 0);
      	oeram: out STD_LOGIC;
      	weram: out STD_LOGIC;
      	triest: out STD_LOGIC
      	
      	);
end component;

component habilitador is	-- Para elegir las habilitaciones
				-- de lectura y escritura entre
				-- los dos subtops
port(
	elige: in STD_LOGIC_VECTOR (1 downto 0);
        orout: out STD_LOGIC;
        proc: in STD_LOGIC;
	imag: in STD_LOGIC
	);
end component;
	
	
component multiplexor is	-- Para elegir de entre las
				-- las direcciones de los dos
				-- subtops
port(
	elige: in STD_LOGIC_VECTOR (1 downto 0);
	dirpro: in STD_LOGIC_VECTOR (14 downto 0);
	dirorig: in STD_LOGIC_VECTOR (14 downto 0);
	dircom: in STD_LOGIC_VECTOR (14 downto 0);
	direccion: out STD_LOGIC_VECTOR (14 downto 0)
	);
end component;


	
signal final,reset,writecom, readcom, zcom, guardada: STD_LOGIC;
signal origproc, nuevaproc, writeproc, readproc, zproc: STD_LOGIC;
signal prodir: STD_LOGIC_VECTOR (15 downto 0);
signal comdir,origdir: STD_LOGIC_VECTOR (14 downto 0);
signal comdato, prodato: STD_LOGIC_VECTOR (7 downto 0);
signal tipomasc: STD_LOGIC_VECTOR (1 downto 0);
begin

COM: topcom
port map(
	P16 => p16,
	P44 => p44,
	P45 => p45,
	P46 => p46,
	P47 => p47,
	P48 => p48,
	P49 => p49,
	P70 => p70,
	P77 => p77,
	P66 => p66,
	P69 => p69,
     	fproc=> final,
      	clk => clk,
      	dirram => comdir,
      	datoraml => busdato,
      	datorame => comdato,
      	GReset => reset,
      	flec => guardada,
      	tipo => tipomasc,
      	oeram => readcom,
      	weram => writecom,
      	triest => zcom
      	
      
      	);

PRO: toptrata
port map(
	clk => clk,
	Rstglobal => reset,
	finproc => final,
	Tammasc => tipomasc,
	inproces => nuevaproc,
	exproces => origproc,
	leeproc => readproc,
	escriproc => writeproc,
	espeorden => guardada,
        P19 => p19,
	P18 => p18,
	P23 => p23,
	P20 => p20,
	P24 => p24,
	P26 => p26,
	P25 => p25,
	dirorig => origdir,
	dirpro => prodir,
        datobien => busdato,
        pixdat => prodato,
        zcontrol => zproc,
        
        coge => open,
	recorre => open, 
	calcmed => open,
	clasmasc => open,
	masqui => open 
 	);
 	
elecread: habilitador -- De la lectura de la RAM
port map(
	elige(1) => origproc, 
        elige(0) => nuevaproc, 
        orout => eread,
        proc => readproc,
	imag => readcom
	);

elecwrite: habilitador	-- De la escritura de la RAM
port map(
	elige(1) => origproc, 
        elige(0) => nuevaproc, 
        orout => ewrite,
        proc => writeproc,
	imag => writecom
	);

elecdir: multiplexor 	-- Para el bus de direcciones
port map(
	elige(1) => origproc,
	elige(0) => nuevaproc,
	dirpro => prodir (14 downto 0),
	dirorig => origdir,
	dircom => comdir,
	direccion => busdirec
	);
	

-- Para el acceso al bus de datos de la RAM en escritura    
bustri:process(zcom,zproc,comdato,prodato)
begin
if (zcom='0') then
		busdato<=comdato;
elsif (zproc='0') then
		busdato<=prodato;
else
		busdato<=(others=>'Z');
end if;
end process;

cs<='0';
end Topglobal_arch;