topcom.vhd

Image_Filter_An_Image_halftone is performed over data loaded into the on board RAM and presented on

--BLOQUE TOP DE LA COMUNICACI覰

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity topcom is
    port (
      	P16: in STD_LOGIC;
	P44: in STD_LOGIC;
	P45: in STD_LOGIC;
	P46: in STD_LOGIC;
	P47: in STD_LOGIC;
	P48: in STD_LOGIC;
	P49: in STD_LOGIC;
	P70: out STD_LOGIC;
	P77: out STD_LOGIC;
	P66: out STD_LOGIC;
	P69: out STD_LOGIC;
     	fproc: in STD_LOGIC;
      	clk: in STD_LOGIC;
      	dirram: out STD_LOGIC_VECTOR (14 downto 0);
      	datoraml: in STD_LOGIC_VECTOR (7 downto 0);
      	datorame: out STD_LOGIC_VECTOR (7 downto 0);
      	GReset: out STD_LOGIC;
      	flec: out STD_LOGIC;
      	tipo: out STD_LOGIC_VECTOR (1 downto 0);
      	oeram: out STD_LOGIC;
      	weram: out STD_LOGIC;
      	triest: out STD_LOGIC
    );
end topcom;

architecture topcom_arch of topcom is
component maqestcom is
  port (
     	addr: in STD_LOGIC_VECTOR(1 downto 0); 
	dout: in STD_LOGIC_VECTOR(7 downto 0); 
	read: in STD_LOGIC; 
	write: in STD_LOGIC; 
	reset: in STD_LOGIC; 
	clk: in STD_LOGIC; 
	fproc: in STD_LOGIC; 
	din: out STD_LOGIC_VECTOR(7 downto 0);
	flec: out STD_LOGIC; 
	datoraml: in STD_LOGIC_VECTOR(7 downto 0); 
     	datorame: out STD_LOGIC_VECTOR(7 downto 0); 
     	tipo: out STD_LOGIC_VECTOR(1 downto 0); 
	oeram: out STD_LOGIC; 
     	weram: out STD_LOGIC; 
	triest: out STD_LOGIC; 
	dirram: out STD_LOGIC_VECTOR(14 downto 0) 
      );

      end component;
      
component sppinterf is
generic (ADDR_SIZE: integer := 2);
    port (
	clk: in STD_LOGIC;
      	reset: out STD_LOGIC;
      	P16: in STD_LOGIC;
	P44: in STD_LOGIC;
	P45: in STD_LOGIC;
	P46: in STD_LOGIC;
	P47: in STD_LOGIC;
	P48: in STD_LOGIC;
	P49: in STD_LOGIC;
	P70: out STD_LOGIC;
	P77: out STD_LOGIC;
	P66: out STD_LOGIC;
	P69: out STD_LOGIC;
      	din: in STD_LOGIC_VECTOR(7 downto 0);
	dout: out STD_LOGIC_VECTOR(7 downto 0);
	addr: out STD_LOGIC_VECTOR(ADDR_SIZE-1 downto 0);
	read: out STD_LOGIC;
	write: out STD_LOGIC
    );
    end component;
 

signal dinaux,doutaux: STD_LOGIC_VECTOR(7 downto 0);
signal addraux: STD_LOGIC_VECTOR(1 downto 0);
signal resetaux,readaux,writeaux: STD_LOGIC;

begin
SPI: sppinterf
	generic map(ADDR_SIZE=>2)
	port map(
	clk =>clk,
      	reset => resetaux,
      	P16 =>P16,
	P44 =>P44,
	P45 =>P45,
	P46 =>P46,
	P47 =>P47,
	P48 =>P48,
	P49 =>P49,
	P70 =>P70,
	P77 =>P77,
	P66 =>P66,
	P69 =>P69,
      	din =>dinaux,
	dout =>doutaux,
	addr =>addraux,
	read => readaux,
	write =>writeaux
	);

MAQEST: maqestcom
port map(
	addr =>addraux,
	dout =>doutaux, 
	read =>readaux, 
	write =>writeaux, 
	reset =>resetaux, 
	clk =>clk,
	fproc =>fproc, 
	din =>dinaux,
	flec =>flec,
	datoraml =>datoraml, 
     	datorame =>datorame, 
     	tipo =>tipo, 
	oeram =>oeram, 
     	weram =>weram, 
	triest =>triest, 
	dirram =>dirram
 	);
GReset<=resetaux;
  
end topcom_arch;