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Logic Analyzer 的代码
shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
-- 2-to-1 multiplexer
COMPONENT mux2to1
PORT ( w0, w1 : IN STD_LOGIC ;
s : IN STD_LOGIC ;
f : OUT STD_L
shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR
cnt8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt8 is
port(clk:in std_logic;
q:out std_logic_vector(2 downto 0));
end cnt8;
architecture behv of cnt8 is
myreg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity myreg is
port(data0:in std_logic_vector(3 downto 0);
data1:in std_logic_vector(3 downto 0);
data2:in std_logic_vector(3 downto 0);
dat
serial_generatedinstance.vhd
--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.serial.generatedInstance
--
-- Author : Michael Mayer (
change.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity change is
port
( period,clk:in std_logic;
n1,n2,n3:in std_logic_vector(3 downto 0);
m1,m2,m3:in std_logi
seri_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seri_2 is
port (clk,start,x: in std_logic;
q: out std_logic_vector(1 downto
select4_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity select4_1 is
port (en: in std_logic;
x_2: in std_logic_vector(1 downto 0)
dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i