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找到约 10,000 项符合
Logic Analyzer 的代码
reg4.vhd
--REG4.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4 IS
PORT(D:IN STD_LOGIC_VECTOR(3 TO 0);
EN,CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 TO 0));
END ENTITY REG4;
piso.vhd
library ieee;
use ieee.std_logic_1164.All;
ENTITY piso IS
PORT(data :IN std_logic_vector(9 DOWNTO 0);
sclk,sl : IN std_logic;
q: OUT STD_LOGIC);
END piso;
ARCHITECTURE
piso.vhd
library ieee;
use ieee.std_logic_1164.All;
ENTITY piso IS
PORT(data :IN std_logic_vector(9 DOWNTO 0);
sclk,sl : IN std_logic;
q: OUT STD_LOGIC);
END piso;
ARCHITECTURE
piso.vhd
library ieee;
use ieee.std_logic_1164.All;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY piso IS
PORT(data :IN std_logic_vector(9 DOWNTO 0);
sl,sclk : IN
ch4_6_1.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************
ch4_4_1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CH4_4_1 IS
PORT ( A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK: IN STD_LOGIC;
RST: IN STD_LOG
ch6_2_4.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************
ctrl.vhd
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxpl
elec_lock.vhd
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxpl
counter60.vhd
--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--****************************