ch6_2_4.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_2_4 is
	PORT(
		 CP, A	: IN	STD_LOGIC;
		 DIF	: OUT   STD_LOGIC;
		 Q		: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0) 
		);
END Ch6_2_4;

--*********************************************
ARCHITECTURE a OF Ch6_2_4 IS
	SIGNAL 	EC, Q1 ,Q2 ,RST :   STD_LOGIC;
	SIGNAL 	QN					: 	STD_LOGIC_VECTOR(3 DOWNTO 0);   
BEGIN
											
		PROCESS (CP,RST)					-- *** COUNTER
		BEGIN
				IF RST = '1' THEN
					QN <= "0000";	
				ELSIF CP'event AND CP='1' THEN
					Q2 <= Q1;	Q1 <= A;	-- TIME DELAY	
					IF EC = '1' THEN
						QN <= QN + 1;		--COUNTER + 1 
					END IF;
				END IF;
		END PROCESS;			

		RST <= 	'1' WHEN QN = 10 ELSE 		-- RESET COUNTER
				'0';		
		
		EC <= Q1 AND NOT Q2;				-- SYNCHRONOUS CONTROL

		DIF <= EC;							-- DIFFERENTIAL OUTPUT

		Q <= QN ;							-- COUNTER OUTPUT			

END a;