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找到约 10,000 项符合
Logic Analyzer 的代码
c_1000.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_1000 is
port(clk:in std_logic;
co:out std_logic);
end c_1000;
architecture rtl of c_1000 is
vgacore..vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgacore is
Port ( clk : in std_logic;
reset : in std_logic;
result.vhd
-- output of CoreGen module generator
-- $Header: romrVHT.vhd,v 1.3 1998/06/15 16:22:02 tonyw Exp $
-- *****************************************************************
-- Copyright 1997-1998 - Xi
radd16.vhd
-- output of CoreGen module generator
-- $Header: adreVHT.vhd,v 1.3 1998/06/15 17:52:34 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
mux4w8.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
rsub16.vhd
-- output of CoreGen module generator
-- $Header: subreVHT.vhd,v 1.3 1998/06/15 17:53:11 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-1
qiangdaqi.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity qiangdaqi is
Port ( clkin : in std_logic;
startin
daoji10.vhd
--倒时时为30秒
--首先是10位倒计时
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity daoji10 is
Port ( EN,clk,rst : in std_logic;
加法器.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
vhdl-jishushizhong.txt
主程序：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity DLED is
port(
CLK1,CLK2: in STD_LOGIC;———————CLK1：时钟记数时钟，CLK2：扫描显示时钟
PUL