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Logic Analyzer 的代码
multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 07.12.2002
--*********
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
CLK_DA
ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,codein: in std_logic;
codeout: out std_logic_vector(1 downto 0));
end;
ar
nco.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
main.vhd
--************************************************************
--
-- Project Name: Timer
-- File Name : main.vhd(top level)
-- Function : This is a basic timer,
-- use 2 key to adjust
keydetc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keydetc is
Port ( clk_5ms :in std_logic;
-- clk_1us :in std_logic;
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------