hdb3.vhd

实现通信过程中的hdb3转换,是通信原理课程中很重要的部分.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,codein: in std_logic;
              codeout: out std_logic_vector(1 downto 0));
end;
architecture behave of hdb3 is

component hdb3_v is            --------------调用hdb3_v函数
port(reset,clk,codein: in std_logic;
              codeout: out std_logic_vector(1 downto 0));
end component;

component hdb3_b is
port(reset,clk: in std_logic;
        codein: in std_logic_vector(1 downto 0);
       codeout: out std_logic_vector(1 downto 0));
end component;

component hdb3_0 is
port(reset,clk: in std_logic;
        codein: in std_logic_vector(1 downto 0);
       codeout: out std_logic_vector(1 downto 0));
end component;
signal d1,d2:std_logic_vector(1 downto 0);
begin
     A: hdb3_v port map(reset,clk,codein,d1);
     B: hdb3_b port map(reset,clk,d1,d2);
     C: hdb3_0 port map(reset,clk,d2,codeout);
end;


-------------------插V实现----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3_v is
port(reset,clk,codein: in std_logic;
              codeout: out std_logic_vector(1 downto 0));
end entity;
architecture behave of hdb3_v is
signal count_0:integer range 0 to 3;
begin
 process(reset,clk,codein) is 
 begin
  if (reset='1') then 
         count_0<=0;codeout<="00";  ---------低电平有效
  elsif(clk'event and clk='1') then
         if codein='0' then
           count_0<=count_0+1;      ---------count_0是0计数器
              if count_0=3 then     ---------连4个0了
                 codeout<="11"; count_0<=0;
              else
                 codeout<="00";     ---------没连4个0
              end if;
         else
            codeout<="01";   ----------------输出1 码
            count_0<=0;   -------------------计数器置0
         end if;
  end if;
 end process;
end;


------------------插B实现----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3_b is
port(reset,clk: in std_logic;
        codein: in std_logic_vector(1 downto 0);
       codeout: out std_logic_vector(1 downto 0));
end;
architecture behave of hdb3_b is
    signal D1,D0       : std_logic_vector(3 downto 0);
    signal flag,count_1: integer range 0 to 1;
begin
 process(clk,codein)is
  begin   
    if(clk'event and clk='1')then
       D1(3)<=codein(1);
       D0(3)<=codein(0);
       D1(2 downto 0)<=D1(3 downto 1);
       D0(2 downto 0)<=D0(3 downto 1);
   end if;
 end process;
 process(reset,clk,D1,D0) is
  begin
    if reset='1' then
        flag<=0;
        count_1<=0;                        ------------count_1是1计数器
    elsif(clk'event and clk='1')then
         if (D1(3)='1' and D0(3)='1')then  ------------输入为V时
            flag<=1;
         else 
            flag<=0;
         end if;
         if(D1(0)='0' and D0(0)='1')then   ------------输入为1时
            count_1<=count_1+1;
         elsif(D1(0)='1' and D0(0)='1')then
            count_1<=0;
         end if;
    end if;
 end process;
process(reset,clk) is
begin
    if reset='1' then 
        codeout<="00";
    elsif(clk='1' and clk'event) then
        if(flag=0 and count_1=0 and (D1(3)='1' and D0(3)='1')) then
            codeout<="10";                 -----------输出为B
        else 
            codeout<=D1(0)&D0(0);
        end if;
    end if;
end process; 
end;   


------------------极性转换实现----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3_0 is
port(reset,clk: in std_logic;
        codein: in std_logic_vector(1 downto 0);
       codeout: out std_logic_vector(1 downto 0));
end entity;
architecture behave of hdb3_0 is
signal even:std_logic;
begin
 process(reset,clk,codein)is
  begin
    if reset='1' then
       even<='0';
       codeout<="00";
    elsif(clk'event and clk='1')then
          if codein="11" then
             if even='1' then   ------------说明前一个非0符号为“-”
                  codeout<="01";------------输出为“-”
             else 
                  codeout<="11";   
             end if;
          elsif(codein="01" or codein="10") then
             if even='1' then 
                  codeout<="11";even<='0';
             else 
                  codeout<="01";even<='1';
             end if;
          else  codeout<="00";
          end if;
    end if;
 end process;
end;