main.vhd

这是关于VHDL时钟的源代码

--************************************************************
--
--			Project Name:	Timer
--			File Name	:	main.vhd(top level)
--			Function	:	This is a basic timer,
--							use 2 key to adjust time,
--							adj use to change mode,
--							up use to make active inc 1
--							four 7-seg led use to display time
--			Writer		:	Dick Hou
--			Date		:	2001/6/1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    Port (	ck	:in std_logic;
			adj		:in std_logic;
			up		:in std_logic;
			com		:out std_logic_vector(3 downto 0);
    		seg		:out std_logic_vector(6 downto 0);
			segdp	:out std_logic
			);
end main;

architecture behavioral of main is
component cnt6bcd is
    Port (	clkin	:in std_logic;
			co		:out std_logic;
    		qout	:out std_logic_vector(2 downto 0)
			);
end component;

component cnt24bcd is
    Port (	clkin	:in std_logic;
    		qout	:out std_logic_vector(5 downto 0)
			);
end component;

component cnt10bcd is
    Port (	clkin	:in std_logic;
			co		:out std_logic;
    		qout	:out std_logic_vector(3 downto 0)
			);
end component;

component bcd2seg is
    Port (	din	:in std_logic_vector(3 downto 0);
    		seg	:out std_logic_vector(6 downto 0)
			);
end component;

component clock is
    Port ( 	clk	:in std_logic;
			clk_1us,clk_5ms,clk_500ms,clk_1s	:out std_logic);
end component;

component keydetc is
    Port (	clk_5ms	:in std_logic;
--			clk_1us	:in std_logic;
    		adj,up	:in std_logic;
			mode	:out std_logic_vector(3 downto 0);
			inc	:out std_logic
		);
end component;

signal	slseg,mlseg	:std_logic_vector(3 downto 0);
signal	shseg,mhseg	:std_logic_vector(2 downto 0);
signal	hseg	:std_logic_vector(5 downto 0);
signal	co	:std_logic_vector(3 downto 0);
signal	common	:std_logic_vector(3 downto 0);
signal	bcdd,bcddin	:std_logic_vector(3 downto 0);
signal 	clk_1us,clk_5ms,clk_500ms,clk_1s	:std_logic;
signal	mode,fl	:std_logic_vector(3 downto 0);
signal	inc,dp		:std_logic;
signal	cks,ckm,ckh	:std_logic;
	
begin
	
	u1:	cnt10bcd port map(cks,co(0),slseg);
	u2: cnt6bcd  port map(co(0),co(1),shseg);
	u3: cnt10bcd port map(ckm,co(2),mlseg);
	u4:	cnt6bcd  port map(co(2),co(3),mhseg);
	u5: cnt24bcd port map(ckh,hseg);
	u6: bcd2seg  port map(bcdd,seg);
	u7: clock	 port map(ck,clk_1us,clk_5ms,clk_500ms,clk_1s);
	u8:	keydetc	 port map(clk_5ms,adj,up,mode,inc);
	process(clk_5ms)
	begin
		if clk_5ms'event and clk_5ms='1' then
			if common="1000" then	common<="0100";
				elsif common="0100" then	common<="0010";
				elsif common="0010" then	common<="0001";
				elsif common="0001" then	common<="1000";
				else  common<="1000";
			 end if;
		end if;
	end process;

	process(clk_500ms)
	begin
		if clk_500ms'event and clk_500ms='1' then
			dp<=not dp;
		end if;
	end process;

	process(dp)
	begin
		if dp='1' then
			fl<="1111";
		else
			fl<="0000";
		end if;
	end process;

	process(common,mode)
	begin
		if mode="0001" then			--normal mode
			if 	common="1000" then bcdd<=mlseg;	segdp<='1';
			elsif common="0100" then bcdd<='0'&mhseg;	segdp<='1';
			elsif common="0010" then bcdd<=hseg(3 downto 0);segdp<=dp;
			elsif common="0001" then bcdd<="00"&hseg(5 downto 4);	segdp<='1';
			else  bcdd<="0000";	segdp<='1';
			end if;
			cks<=clk_1s;
			ckm<=co(1);
			ckh<=co(3);
			
		elsif mode="0010" then		--adjust secode
				segdp<='1';
				if  common="1000" then bcdd<=slseg or fl;
				elsif common="0100" then bcdd<=('0'&shseg) or fl;
				elsif  common="0010" then bcdd<="1111";	
				else	bcdd<="1111";
				end if;
			cks<=inc or clk_1s;
			ckm<=co(1);
			ckh<=co(3);

		elsif mode="0100" then		--adjust minute
				if common="1000" then bcdd<=mlseg or fl;	segdp<='1';
				elsif common="0100" then bcdd<=('0'&mhseg) or fl;	segdp<='1';
				elsif common="0010" then bcdd<=hseg(3 downto 0);	segdp<=dp;
				elsif common="0001" then bcdd<="00"&hseg(5 downto 4);	segdp<='1';
				else  bcdd<="0000";	segdp<='1';
				end if;
			cks<=clk_1s;
			ckm<=inc or co(1);
			ckh<=co(3);
		elsif mode="1000" then		--adjust hour
				if common="1000" then bcdd<=mlseg;	segdp<='1';
				elsif common="0100" then bcdd<='0'&mhseg;	segdp<='1';
				elsif common="0010" then bcdd<=hseg(3 downto 0) or fl;	segdp<=dp;
				elsif common="0001" then bcdd<=("00"&hseg(5 downto 4))or fl; segdp<='1';
				else  bcdd<="0000";	segdp<='1';
				end if;	
			cks<=clk_1s;
			ckm<=co(1);
			ckh<=inc or co(3);
		end if;
	end process;
	com<=common;

end behavioral;