nco.vhd

基于VHDL的DDS设计

 -----------------------------------------------------------------------------                                                                     
 -- Project Name         : NCO                                            
 --                                                                             
 -- Author               : Bluetea
 -- Creation Date        : 03/11/04 18:20:21                                              
 -- Version Number       : 1.0                                                                                                                                                                                             
 -- Description          :                                                                                                                                  
 -- This is the top level of the Direct Digital Synthesizer.
 -----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY NCO IS
       PORT(
             RESETN     : IN  STD_LOGIC;				     -- global reset
             SYSCLK     : IN  STD_LOGIC;                     -- system clock
             FREQWORD   : IN  STD_LOGIC_VECTOR (31 DOWNTO 0);-- input frequency word from external pins
	         FWWRN      : IN  STD_LOGIC;					 -- low asserted frequency word write strobe
	         PHASEWORD  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); -- input phase word from external pins
	         PWWRN      : IN  STD_LOGIC;                     -- low asserted frequency word write strobe
	         COS        : OUT  STD_LOGIC;                    -- digital cos output
	         SIN        : OUT  STD_LOGIC;                    -- digital sin output
	         MCOS       : OUT  STD_LOGIC;                    -- modulated digital cos output
	         MSIN       : OUT  STD_LOGIC;                    -- modulated digital sin output
	         NCOOUT     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  -- NCO output of sin wave
          );
END NCO;

ARCHITECTURE top OF NCO IS
    SIGNAL syncfreq	    : STD_LOGIC_VECTOR (31 DOWNTO 0);  -- synchronous frequency word
    SIGNAL syncphswd	: STD_LOGIC_VECTOR (7 DOWNTO 0);   -- synchronous phase word
    SIGNAL phase	    : STD_LOGIC_VECTOR (7 DOWNTO 0);   -- phase output from phase accumulator
    SIGNAL modphase     : STD_LOGIC_VECTOR (7 DOWNTO 0);   -- modulated phase value after phase mod block

    COMPONENT loadfw PORT(SYSCLK    : IN  STD_LOGIC;                     
                          RESETN    : IN  STD_LOGIC; 			         
                          FWWRN     : IN  STD_LOGIC; 			         
                          FREQWORD  : IN  STD_LOGIC_VECTOR (31 DOWNTO 0); 
                          SYNCFREQ  : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
    END COMPONENT;
    COMPONENT loadpw PORT(SYSCLK    : IN  STD_LOGIC;                     
                          RESETN    : IN  STD_LOGIC; 			         
                          PWWRN     : IN  STD_LOGIC; 			         
                          PHASEWORD : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); 
                          SYNCPHSWD : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END COMPONENT;
    COMPONENT phasea PORT(SYSCLK    : IN  STD_LOGIC;                     
                          RESETN    : IN  STD_LOGIC; 			         		         
                          SYNCFREQ  : IN  STD_LOGIC_VECTOR (31 DOWNTO 0); 
                          COS       : OUT STD_LOGIC;
                          SIN       : OUT STD_LOGIC;
                          PHASE     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END COMPONENT;
    COMPONENT phasemod PORT(SYSCLK    : IN  STD_LOGIC;                     
                            RESETN    : IN  STD_LOGIC; 			         		         
                            SYNCPHSWD : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); 
                            PHASE     : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
                            MCOS      : OUT STD_LOGIC;
                            MSIN      : OUT STD_LOGIC;
                            MODPHASE  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END COMPONENT;
    COMPONENT sinlup PORT(SYSCLK    : IN  STD_LOGIC;                     
                          RESETN    : IN  STD_LOGIC; 			         	         
                          MODPHASE  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); 
                          NCOOUT    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END COMPONENT;

--------------------------------------------------------------------
BEGIN
    U_loadfw   : loadfw    PORT MAP(SYSCLK,RESETN,FWWRN,FREQWORD,syncfreq);
    U_loadpw   : loadpw    PORT MAP(SYSCLK,RESETN,PWWRN,PHASEWORD,syncphswd);
    U_phasea   : phasea    PORT MAP(SYSCLK,RESETN,syncfreq,COS,SIN,phase);
    U_phasemod : phasemod  PORT MAP(SYSCLK,RESETN,syncphswd,phase,MCOS,MSIN,modphase);
    U_sinlup   : sinlup    PORT MAP(SYSCLK,RESETN,modphase,NCOOUT);

END top;