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Logic Analyzer 的代码
cnt_12.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_12 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
cnt_10.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_10 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
cnt_60.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_60 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
cnt_60.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_60 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
cnt_10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_10 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
cpu1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity cpu1 is
port(clk:in std_logic;
rst:in std_logic
video.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------**********************************************-----------------------
ENTITY VIDEO IS
PORT(
reg.vhd
-- reg.vhd
-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. T
pc.vhd
-- pc.vhd
-- This module implements the 16-bit program Counter (PC). PC is loaded from
-- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to
-- zero when "reset" is assert
cfg_regs.vhd
--*****************************************************************************
-- FILE : PCI_CFGREG
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Configuration Space