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Logic Analyzer 的代码
mx_7821.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mx_7821 is
port (clk: in std_logic;
din: in std_logic_vector (7 downto
mux6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux6 is
port(cnthh,cnthl,cntmh,cntml,cntsh,cntsl: in std
mux6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux6 is
port(cnthh,cnthl,cntmh,cntml,cntsh,cntsl: in std
sdr_sdram.vhd
library ieee;
use ieee.std_logic_1164.all;
entity sdr_sdram is
generic (
ASIZE : integer := 22;
DSIZE : integer := 32;
ROWSIZE
fifo_tb.vhd
--********************************************************************
--* This automatically generated Test Bench template has been created*
--* By ACTIVE-HDL . Copyright (C) ALDEC
uart_clock.vhd
--
-- KCPSM3 reference design - Real Time Clock with UART communications
--
-- Ken Chapman - Xilinx Ltd - October 2003
--
-- The design demonstrates the following:-
-- Connection of KC
display.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(disclk:in std_logic;
num1:in std_logic_vector(3 downto 0);
num2:in std_logic_vector(3
display.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(disclk:in std_logic;
num1:in std_logic_vector(3 downto 0);
num2:in std_logic_vector(3
crcgen.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity CRCGEN is
port(
SD :in std_logic;
CLRN :in std_logic;
SFT :in std_logic;
CRC :out std_logic_vector(7 downto 0);
clk :in
ide.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 01/30/2006
-- Copyright : 2006, XESS C