mux6.vhd

数字钟的VHDL源程序

library ieee;
use ieee.std_logic_1164.all;                        
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mux6 is
port(cnthh,cnthl,cntmh,cntml,cntsh,cntsl: in std_logic_vector(3 downto 0);
       cp1,reset:in std_logic;
     set: out std_logic_vector(2 downto 0);
     cntout: out std_logic_vector(3 downto 0)
);
end mux6;
architecture behav of mux6 is
  signal sel:std_logic_vector(2 downto 0);
begin
set<=sel;
process(cp1,reset)
begin
    if (reset='0') then
        sel<="000";
    elsif (cp1'event and cp1='1') then
       if (sel>="101") then
       sel<="000";
       else sel<=sel+1;
       end if;
    end if;
        case sel is
       when "000"=>cntout<=cntsl(3 downto 0);
       when "001"=>cntout<=cntsh(3 downto 0);
       when "010"=>cntout<=cntml(3 downto 0);
       when "011"=>cntout<=cntmh(3 downto 0);
       when "100"=>cntout<=cnthl(3 downto 0);
       when "101"=>cntout<=cnthh(3 downto 0);
       when others=>cntout<="0000";
    end case;
end process;
end behav;