📄 sdr_sdram.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity sdr_sdram is
generic (
ASIZE : integer := 22;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 8;
BANKSIZE : integer := 2;
ROWSTART : integer := 8;
COLSTART : integer := 0;
BANKSTART : integer := 20
);
port (
-- PM : OUT STD_LOGIC;
-- OE1 : out std_logic;
CLK : in std_logic; --System Clock
RESET_N : in std_logic; --System Reset
ADDR : in std_logic_vector(ASIZE-1 downto 0); --Address for controller requests
CMD : in std_logic_vector(2 downto 0); --Controller command
CMDACK : out std_logic; --Controller command acknowledgement
DATAIN : in std_logic_vector(DSIZE-1 downto 0); --Data input
IDATAOUT : out std_logic_vector(DSIZE-1 downto 0); --Data output
--DM : in std_logic_vector(DSIZE/8-1 downto 0); --Data mask input
ISA : out std_logic_vector(11 downto 0); --SDRAM address output
IBA : out std_logic_vector(1 downto 0); --SDRAM bank address
--ICKE : out std_logic; --SDRAM clock enable
IRAS_N : out std_logic; --SDRAM Row address Strobe
ICAS_N : out std_logic; --SDRAM Column address Strobe
IWE_N : out std_logic; --SDRAM write enable
IDQ : inout std_logic_vector(DSIZE-1 downto 0); --SDRAM data bus
-- DQM : out std_logic_vector(DSIZE/8-1 downto 0); --SDRAM data mask lines
IDATAVALIDTEMP : out std_logic
);
end sdr_sdram;
architecture RTL of sdr_sdram is
-- component declarations
component command
generic (
ASIZE : integer := 22;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 8;
BANKSIZE : integer := 2;
ROWSTART : integer := 8;
COLSTART : integer := 0;
BANKSTART : integer := 20 -- Starting position of the bank address within ADDR
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
SADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address
NOP : in std_logic; -- Decoded NOP command
READA : in std_logic; -- Decoded READA command
WRITEA : in std_logic; -- Decoded WRITEA command
REFRESH : in std_logic; -- Decoded REFRESH command
PRECHARGE : in std_logic; -- Decoded PRECHARGE command
LOAD_MODE : in std_logic; -- Decoded LOAD_MODE command
SC_CL : in std_logic_vector(1 downto 0); -- Programmed CAS latency
SC_RC : in std_logic_vector(1 downto 0); -- Programmed RC delay
SC_RRD : in std_logic_vector(3 downto 0); -- Programmed RRD delay
SC_PM : in std_logic; -- programmed Page Mode
SC_BL : in std_logic_vector(3 downto 0); -- Programmed burst length
REF_REQ : in std_logic; -- Hidden refresh request
REF_ACK : out std_logic; -- Refresh request acknowledge
CM_ACK : out std_logic; -- Command acknowledge
OE : out std_logic; -- OE signal for data path module
SA : out std_logic_vector(11 downto 0); -- SDRAM address
BA : out std_logic_vector(1 downto 0); -- SDRAM bank address
--CKE : out std_logic; -- SDRAM clock enable
RAS_N : BUFFER std_logic; -- SDRAM RAS
CAS_N : BUFFER std_logic; -- SDRAM CAS
WE_N : BUFFER std_logic; -- SDRAM WE_N
DATAVALID : out std_logic
);
end component;
component sdr_data_path
generic (
DSIZE : integer := 32
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
OE : in std_logic; -- Data output(to the SDRAM) enable
DATAIN : in std_logic_vector(DSIZE-1 downto 0); -- Data input from the host
IDATAVALID : in std_logic;
-- DM : in std_logic_vector(DSIZE/8-1 downto 0); -- byte data masks
DATAOUT : out std_logic_vector(DSIZE-1 downto 0); -- Read data output to host
DQIN : in std_logic_vector(DSIZE-1 downto 0); -- SDRAM data bus
DQOUT : out std_logic_vector(DSIZE-1 downto 0);
DATAVALIDTEMP : out std_logic
-- DQM : out std_logic_vector(DSIZE/8-1 downto 0) -- SDRAM data mask ouputs
);
end component;
component control_interface
generic (
ASIZE : integer := 22
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
CMD : in std_logic_vector(2 downto 0); -- Command input
ADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address
REF_ACK : in std_logic; -- Refresh request acknowledge
CM_ACK : in std_logic; -- Command acknowledge
NOP : out std_logic; -- Decoded NOP command
READA : out std_logic; -- Decoded READA command
WRITEA : out std_logic; -- Decoded WRITEA command
REFRESH : out std_logic; -- Decoded REFRESH command
PRECHARGE : out std_logic; -- Decoded PRECHARGE command
LOAD_MODE : out std_logic; -- Decoded LOAD_MODE command
SADDR : out std_logic_vector(ASIZE-1 downto 0); -- Registered version of ADDR
SC_CL : out std_logic_vector(1 downto 0); -- Programmed CAS latency
SC_RC : out std_logic_vector(1 downto 0); -- Programmed RC delay
SC_RRD : out std_logic_vector(3 downto 0); -- Programmed RRD delay
SC_PM : out std_logic; -- programmed Page Mode
SC_BL : out std_logic_vector(3 downto 0); -- Programmed burst length
REF_REQ : out std_logic; -- Hidden refresh request
CMD_ACK : out std_logic -- Command acknowledge
);
end component;
-- signal declarations
signal SA : std_logic_vector(11 downto 0); --SDRAM address output
signal BA : std_logic_vector(1 downto 0); --SDRAM bank address
--signal CKE : std_logic; --SDRAM clock enable
signal RAS_N : std_logic; --SDRAM Row address Strobe
signal CAS_N : std_logic; --SDRAM Column address Strobe
signal WE_N : std_logic;
signal DQIN : std_logic_vector(DSIZE-1 downto 0);
signal DATAOUT : std_logic_vector(DSIZE-1 downto 0);
signal DQOUT : std_logic_vector(DSIZE-1 downto 0); --SDRAM write enable
signal saddr : std_logic_vector(ASIZE-1 downto 0);
signal sc_cl : std_logic_vector(1 downto 0);
signal sc_rc : std_logic_vector(1 downto 0);
signal sc_rrd : std_logic_vector(3 downto 0);
signal sc_pm : std_logic;
signal sc_bl : std_logic_vector(3 downto 0);
signal load_mode : std_logic;
signal nop : std_logic;
signal reada : std_logic;
signal writea : std_logic;
signal refresh : std_logic;
signal precharge : std_logic;
signal oe : std_logic;
signal ref_req : std_logic;
signal ref_ack : std_logic;
signal cm_ack : std_logic;
signal datavalid : std_logic;
signal idatavalid : std_logic;
signal datavalidtemp :std_logic;
begin
-- instantiate the control interface module
control1 : control_interface
generic map (
ASIZE => ASIZE
)
port map (
CLK => CLK,
RESET_N => RESET_N,
CMD => CMD,
ADDR => ADDR,
REF_ACK => ref_ack,
CM_ACK => cm_ack,
NOP => nop,
READA => reada,
WRITEA => writea,
REFRESH => refresh,
PRECHARGE => precharge,
LOAD_MODE => load_mode,
SADDR => saddr,
SC_CL => sc_cl,
SC_RC => sc_rc,
SC_RRD => sc_rrd,
SC_PM => sc_pm,
SC_BL => sc_bl,
REF_REQ => ref_req,
CMD_ACK => CMDACK
);
-- instantiate the command module
command1 : command
generic map(
ASIZE => ASIZE,
DSIZE => DSIZE,
ROWSIZE => ROWSIZE,
COLSIZE => COLSIZE,
BANKSIZE => BANKSIZE,
ROWSTART => ROWSTART,
COLSTART => COLSTART,
BANKSTART => BANKSTART
)
port map (
CLK => CLK,
RESET_N => RESET_N,
SADDR => saddr,
NOP => nop,
READA => reada,
WRITEA => writea,
REFRESH => refresh,
PRECHARGE => precharge,
LOAD_MODE => load_mode,
SC_CL => sc_cl,
SC_RC => sc_rc,
SC_RRD => sc_rrd,
SC_PM => sc_pm,
SC_BL => sc_bl,
REF_REQ => ref_req,
REF_ACK => ref_ack,
CM_ACK => cm_ack,
OE => oe,
SA => SA,
BA => BA,
-- CKE => CKE,
RAS_N => RAS_N,
CAS_N => CAS_N,
WE_N => WE_N,
DATAVALID => DATAVALID
);
-- instantiate the data path module
data_path1 : sdr_data_path
generic map (
DSIZE => DSIZE
)
port map (
CLK => CLK,
RESET_N => RESET_N,
OE => oe,
DATAIN => DATAIN,
-- DM => DM,
DATAOUT => DATAOUT,
-- DQM => DQM,
DQIN => DQIN,
DQOUT => DQOUT,
IDATAVALID => IDATAVALID,
DATAVALIDTEMP => DATAVALIDTEMP
);
-- Add a level flops to the sdram i/o that can be place
-- by the router into the I/O cells
process(CLK)
begin
if rising_edge(CLK) then
ISA <= SA;
IBA <= BA;
--ICKE <= CKE;
IRAS_N <= RAS_N;
ICAS_N <= CAS_N;
IWE_N <= WE_N;
DQIN <= IDQ;
IDATAOUT <= DATAOUT;
IDATAVALID <= DATAVALID;
IDATAVALIDTEMP <= DATAVALIDTEMP;
end if;
end process;
-- tri-state the data bus using the OE signal from the main controller.
IDQ <= DQOUT when OE = '1' else (others => 'Z');
---写操作流程DATAIN-DQOUT-DQ，OE=1时的数据为写到 sdram的 有效数据
--OE1 <= OE;
--PM <= SC_PM;
end RTL;
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