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Logic Analyzer 的代码
car.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY car IS
PORT(
iSensorState:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
CLRn,clkin:IN STD_LOGIC;
Dcl
scan4digit.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:16:45 11/20/2008
-- Design Name:
-- Module Name: Scan4Digit
lms.vhd
-- FileName:LMS.vhd
-- Purpose: LMS arithmetic Module .
-- Last updated: 2005.7.10
---------------------------------------------------------------------------------------------------
-----
nco.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
result.vhd
-- output of CoreGen module generator
-- $Header: romrVHT.vhd,v 1.3 1998/06/15 16:22:02 tonyw Exp $
-- *****************************************************************
-- Copyright 1997-1998 - Xi
radd16.vhd
-- output of CoreGen module generator
-- $Header: adreVHT.vhd,v 1.3 1998/06/15 17:52:34 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
mux4w8.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
rsub16.vhd
-- output of CoreGen module generator
-- $Header: subreVHT.vhd,v 1.3 1998/06/15 17:53:11 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-1
ssram.vhd
--
--
-- S S R A M i n t e r f a c e
--
-- various components for ssrams
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package SSRAM is
component ssram_conn is
gener
pcit_core.vhd
--*****************************************************************************
--* *
--* EuCore PCI-T32 - PCI Ta