radd16.vhd

fast fourior transform

-- output of CoreGen module generator
-- $Header: adreVHT.vhd,v 1.3 1998/06/15 17:52:34 tonyw Exp $
-- ************************************************************************
--  Copyright 1996-1998 - Xilinx, Inc.
--  All rights reserved.
-- ************************************************************************
--
--  Description:
--  4K Non-Loadable Adder
--  

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library xul;
use xul.ul_utils.all;


ENTITY radd16 IS
  PORT( a : IN  std_logic_vector( 16 - 1 DOWNTO 0 );
        b : IN  std_logic_vector( 16 - 1 DOWNTO 0 );
        c : IN  std_logic;
        ce : IN  std_logic;
        ci : IN  std_logic;
        clr : IN  std_logic;
        s : OUT std_logic_vector( 16 DOWNTO 0 ));
END radd16;

ARCHITECTURE behv OF radd16 IS
CONSTANT w: integer := 16;
CONSTANT signed : boolean := true;

FUNCTION plus (a, b : std_logic_vector;
	       cin: std_logic;
	       width : integer) RETURN std_logic_vector IS
VARIABLE retval : std_logic_vector(width-1 DOWNTO 0);
VARIABLE carry : std_logic := cin;
BEGIN  -- plus
  IF (anyX(a) OR anyX(b) OR rat(cin) = 'X') THEN
      retval := (OTHERS => 'X');
  else
      FOR i IN 0 TO width-1 LOOP
	  retval(i) := a(i) XOR b(i) XOR carry;
	  carry := (a(i) AND b(i)) or
		   (a(i) AND carry) or
		   (b(i) AND carry);
      END LOOP;  -- i
  END IF;    
  RETURN retval;
END plus;

BEGIN
 process (c, clr)
   variable sum : std_logic_vector(w DOWNTO 0) := (OTHERS => '0');
   begin
     if (rat(clr) = 'X') then
       sum := (OTHERS => 'X');
     elsif (rat(clr) = '1') then
       sum := (OTHERS => '0');
     elsif (rat(c) = 'X' AND rat(c'last_value)/='X' AND rat(ce) /= '0') then
       sum := (OTHERS => 'X');
     elsif (c'event and rat(c) = '1' and rat(c'last_value) = '0') then
       if (rat(ce) = 'X') then
         sum := (OTHERS => 'X');
       elsif (rat(ce) = '1') then
         if(rat(ci) = 'X' OR anyX(a) OR anyX(b)) then
           sum := (OTHERS => 'X');
         else
           sum := plus(extend(a, w+1, signed), extend(b, w+1, signed), ci, w+1);
         end if;
       end if;
     end if; 
   s <= sum;
   end process;
end behv;