📄 lms.vhd
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-- FileName:LMS.vhd
-- Purpose: LMS arithmetic Module .
-- Last updated: 2005.7.10
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.PCK_S2V.ALL;
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ENTITY LMS IS
PORT (
waveIN : OUT std_logic_vector(7 DOWNTO 0);
waveOut : OUT std_logic_vector(7 DOWNTO 0);
eOut : OUT std_logic_vector(7 DOWNTO 0);
start : IN std_logic;
CLK : IN std_logic
);
END LMS;
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ARCHITECTURE Behav OF LMS IS
COMPONENT cosfunc PORT ( THETA : IN std_logic_vector(5 downto 0); CLK : IN std_logic; ACLR : IN std_logic;
ND : IN std_logic; RFD : OUT std_logic; RDY : OUT std_logic;
SINE : OUT std_logic_vector(7 downto 0); COSINE : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT costest PORT ( THETA : IN std_logic_vector(5 downto 0); CLK : IN std_logic; ACLR : IN std_logic;
ND : IN std_logic; RFD : OUT std_logic; RDY : OUT std_logic;
SINE : OUT std_logic_vector(7 downto 0)
);END COMPONENT;---------------------------------------------------------------------------------------------------
SIGNAL sTHETA : std_logic_vector(5 DOWNTO 0);
SIGNAL CosOut : std_logic_vector(7 DOWNTO 0);
SIGNAL SinOut : std_logic_vector(7 DOWNTO 0); SIGNAL err : SIGNED(7 DOWNTO 0); SIGNAL ACLR : std_logic;
SIGNAL Wcos : SIGNED(9 DOWNTO 0);
SIGNAL Wsin : SIGNED(9 DOWNTO 0);
SIGNAL Qcos : SIGNED(9 DOWNTO 0);
SIGNAL Qsin : SIGNED(9 DOWNTO 0);
SIGNAL ND : std_logic;
SIGNAL RFD : std_logic; SIGNAL RDY : std_logic;
SIGNAL TestRFD : std_logic; SIGNAL TestRDY : std_logic;
SIGNAL waveINPUT : std_logic_vector(7 DOWNTO 0);
SIGNAL THETA : std_logic_vector(5 DOWNTO 0);
SIGNAL INT_THETA : INTEGER RANGE 0 TO 63;
SIGNAL INT_sTHETA : INTEGER RANGE 0 TO 63;
--------------------------------------------------------------------------------------------------------------------------------
BEGIN
U1 : cosfunc PORT MAP (
THETA => sTHETA, CLK => CLK, ACLR => ACLR,
ND => ND, RFD => RFD, RDY => RDY,
SINE => SinOut, COSINE => CosOut
); U2 : costest PORT MAP ( THETA => THETA, CLK => CLK, ACLR => ACLR,
ND => ND, RFD => TestRFD, RDY => TestRDY,
SINE => waveINPUT
);
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----- Generate THETA/sTHETA used as an input of COS/SIN IP CORE ---------
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GenerateTHETA:PROCESS
BEGIN
WAIT UNTIL ( clk'EVENT AND clk='1' );
IF(start = '1') THEN
ACLR <= '0';
ND <= '1';
INT_sTHETA <= INT_sTHETA+1;
sTHETA <= CONV_STD_LOGIC_VECTOR(INT_sTHETA,6);
INT_THETA <= INT_THETA+1;
THETA <= CONV_STD_LOGIC_VECTOR(INT_THETA,6);
ELSE
ACLR <= '1';
ND <= '1';
INT_sTHETA <= 0;
INT_THETA <= 8;
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------
Generate_Wcos:PROCESS
VARIABLE Tcos: SIGNED(15 DOWNTO 0);
BEGIN
WAIT UNTIL ( clk'EVENT AND clk='1' );
IF(start = '1' AND RDY = '1' AND TestRDY = '1') THEN
Tcos := SIGNED(err)*SIGNED(CosOut); -- XX.XXXXXX * XX.XXXXXX
Tcos(14 DOWNTO 0) := Tcos(15 DOWNTO 1); -- Cyc Right Shift = *0.5
Wcos <= Wcos + SIGNED(Tcos(15 DOWNTO 6)); -- XXXX.XXXX XX|xxxx
ELSE
Wcos <= "0001000000"; -- XXXX.XXXXXX ; default value = 0001.000000
END IF;
END PROCESS;
Generate_Wsin:PROCESS
VARIABLE Tsin: SIGNED(15 DOWNTO 0);
BEGIN
WAIT UNTIL ( clk'EVENT AND clk='1' );
IF(start = '1' AND RDY = '1' AND TestRDY = '1') THEN -- "start" signal.
Tsin :=SIGNED(err)*SIGNED(SinOut);
Tsin(14 DOWNTO 0) := Tsin(15 DOWNTO 1);
Wsin <= Wsin + SIGNED(Tsin(15 DOWNTO 6));
ELSE
Wsin <= "0001000000";
END IF;
END PROCESS;
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-----------------------------------------------------------------------------------------------------
GenerateQcos:PROCESS
VARIABLE cosTemp: SIGNED(17 DOWNTO 0);
BEGIN
WAIT UNTIL ( clk'EVENT AND clk='1' );
IF(start = '1' AND RDY = '1' AND TestRDY = '1') THEN
cosTemp := SIGNED(Wcos)*SIGNED(CosOut); -- XXXX.XXXXXX * XX.XXXXXX = xxXXXX.XX XXXXxxxx xx
Qcos <= SIGNED(cosTemp(15 DOWNTO 6));
ELSE
Qcos <= "0000000000";
END IF;
END PROCESS;
GenerateQsin:PROCESS
VARIABLE sinTemp: SIGNED(17 DOWNTO 0);
BEGIN
WAIT UNTIL ( clk'EVENT AND clk='1' );
IF(start = '1' AND RDY = '1' AND TestRDY = '1' ) THEN
sinTemp := SIGNED(Wsin)*SIGNED(SinOut);
Qsin <= SIGNED(sinTemp(15 DOWNTO 6));
ELSE
Qsin <= "0001000000";
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------------------------------------------
GenerateErr:PROCESS
VARIABLE Temp: SIGNED(9 DOWNTO 0);
BEGIN
WAIT UNTIL ( clk'EVENT AND clk='1' );
IF(start = '1' AND RDY = '1' AND TestRDY = '1' ) THEN
Temp := Qcos + Qsin; -- -1<= ( XXXX.XXXXXX + XXXX.XXXXXX = xxXX.XXXXXX) <= 1
waveOut <= FuncS2V(SIGNED(Temp(7 DOWNTO 0)));
err <= SIGNED(waveINPUT) - SIGNED(Temp(7 DOWNTO 0));
eOut <= FuncS2V(err);
ELSE
err <= "01000000";
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------------------------------------------
waveIN <= waveINPUT;
--------------------------------------------------------------------------------------------------------------------------------
END Behav;
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