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Logic Analyzer 的代码
lcd1602.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************
omet.vhd
--omet.vhd
--v0.1
--measure dff
library ieee;
use ieee.std_logic_1164.all;
entity omet is
port(
clk: in std_logic;
reset: in std_logic;
imet_0: in std_logic_vector(5 downto 0);
txunit.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
nco.cmp
-- Generated by NCO 2.2.2 [Altera, IP Toolbench v1.2.7 build38]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- *******
produce.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity produce is
port(
clk:in std_logic; --时钟
set:in std_logic; --预制
reset:in std_logic; --复位
pro.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pro is
port(
clk:in std_logic; --时钟
set:in std_logic; --预置
reset:in std_logic; --复位
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
vga_main.vhd
---------------------------------------------------------------------
-- vga_main.vhd Demo VGA configuration module.
---------------------------------------------------------------------
-- Autho