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Logic Analyzer 的代码
相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
sha1_fa.vhd
------------------------------------------------------------------------
--
-- Single-bit adder
--
------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_
componentslib.vhd
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--组原 Group 6;
--顶层数据包
--将各个模块(ALU,Q_REG,RAM_
ureg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ureg is
port (
clk, reset, load: in std_logic;
d : in std_logic_vector(15 downto 0)
myregslibrary.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package myregslibrary is
constant size : integer := 16;
component rdff
port (clk,reset : in std_logic;
d
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
ch4_6_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch4_6_1 is
port(
dataout:out std_logic_vector(6 downto 0);
addr :in
只读存储器.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch4_6_1 is
port(
dataout:out std_logic_vector(6 downto 0);
addr :in
reg_8rst.vhd
-- "reg_8rst.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gene