myregslibrary.vhd

来自「组成原理的大作业」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package myregslibrary is
constant size : integer := 16;
component rdff
port (clk,reset : in std_logic;
         d         : in std_logic_vector(size-1 downto 0);
         q 		   : buffer std_logic_vector(size-1 downto 0)
      );
end component;
component rdff1
port (
       clk,reset : in std_logic;
       d : in std_logic;
       q : buffer std_logic
      );
end component;
component rreg
port (
       clk, reset, load : in std_logic;
       d                : in std_logic_vector(size-1 downto 0);
       q                : buffer std_logic_vector(size-1 downto 0)
      );
end component;
component rreg1
port (
       clk, reset, load : in std_logic;
       d                : in std_logic;
       q                : buffer std_logic);
end component;
component reg
port (
       clk,load,rst,pst : in std_logic;
       d                : in std_logic_vector(size-1 downto 0);
       q                : buffer std_logic_vector(size-1 downto 0)
      );
end component;
component ureg
port (
       clk, reset, load : in std_logic;
       d                : in std_logic_vector(size-1 downto 0);
       q                : buffer std_logic_vector(size-1 downto 0)
      );
end component;
end myregslibrary;