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找到约 10,000 项符合
Logic Analyzer 的代码
lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --4MHZ FROM D12
Reset
timer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TIMER IS
PORT( iclk : IN STD_LOGIC; --input clock
iRst : IN STD_LOGIC;
iNF: IN STD_LOGIC;
timer.vhd.bak
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TIMER IS
PORT( iclk : IN STD_LOGIC; --input clock
iRst : IN STD_LOGIC;
iNF: IN STD_LOGIC;
iSMin: IN STD_
ddfs.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY ddfs IS
PORT (clk,P12 : IN Std_logic;
P13: INOUT Std_logic;
wr: OUT Std_logic;
da
counter.vhd
library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;
entity counter is
generic(n: NATURAL := 16);
port( clock: in std_logic;
reset: in std_logic;
se
keywatch.vhd
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use unisim.vcomponents.all;
use work.key_Inter_pckg.all;
entity KeyWatch is --100_000
generic(FREQ : natural := 50000 );
keytx.vhd
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use unisim.vcomponents.all;
use work.key_Inter_pckg.all;
entity KeyTx is --100_000
generic(FREQ : natural := 50000 );
keyvga.vhd
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.key_Inter_pckg.all;
--library unisim;
--use unisim.
topkbwatch.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopKbWatch is
Port ( clk,ps2_data,ps2_clk : in STD_LOGIC;
SW7,SW6,SW5,SW
加法器源程序.txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log