代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/221864/14717372

vhd mc8051_ram_.vhd

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www.eeworm.com/read/221864/14717394

vhd alumux_.vhd

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www.eeworm.com/read/221864/14717429

vhd mc8051_alu_.vhd

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www.eeworm.com/read/221864/14717437

vhd mc8051_siu_.vhd

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www.eeworm.com/read/220322/14842379

vhd cnt10.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT(CLK:IN STD_LOGIC; RST:IN STD_LOGIC; EN:IN STD_LOGIC; OUTX:OUT STD_LOGIC_VECT
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www.eeworm.com/read/220322/14842701

vhd cnt10.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT(CLK:IN STD_LOGIC; RST:IN STD_LOGIC; EN:IN STD_LOGIC; OUTX:OUT STD_LOGIC_VECT
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www.eeworm.com/read/218836/14904695

vhd program-m.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity newminute is port (carry,reset,clk1:in std_logic; sethour: in std_logic :='0'; Lmin,Hmin: out
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www.eeworm.com/read/218836/14904701

vhd program-h.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity newhour is port (carrym,reset:in std_logic; Hhour,Lhour: out std_logic_vector(3 downto 0)); end newho
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www.eeworm.com/read/216963/14983995

vhd xil_rgb2ycrcb_sg_wrap.vhd

--******************************************************************* -- Copyright(C) 2005 by Xilinx, Inc. All rights reserved. -- This text/file contains proprietary, confidential -- information of X
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www.eeworm.com/read/216955/14984351

vhd counter.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER IS PORT( CLK:IN STD_LOGIC; EN: IN STD_LOGIC; S: IN STD_LOGIC; LOAD: IN STD_LOGI
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