cnt10.vhd

用VHDL 语言描述频率计的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
  PORT(CLK:IN STD_LOGIC;
       RST:IN STD_LOGIC;
       EN:IN STD_LOGIC;
	   OUTX:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	   OUTY:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE ONE OF CNT10 IS
  SIGNAL SS:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  PROCESS(CLK,RST,EN)
    BEGIN
      IF RST='1'THEN SS<="0000";OUTY<='0';
      ELSIF CLK'EVENT AND CLK='1'THEN 
         IF EN='1' THEN
            IF SS="1001" THEN SS<="0000";OUTY<='1';
            ELSE SS<=SS+1;OUTY<='0';
         END IF;
      END IF;
     END IF;
    OUTX<=SS;
   END PROCESS;
   END ONE;