sm.map.summary

来自「用VHDL 语言描述频率计的设计」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sun Jun 17 22:28:30 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : SM
Top-level Entity Name : SM
Family : Cyclone
Total logic elements : 7
Total pins : 12
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0