代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/226702/14454325
vhd sum99.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum99 is
port(k: in std_logic_vector(9 downto 0);
clk: in std_logic;
en: in std_logic;
reset: i
www.eeworm.com/read/226179/14490769
tdf count60.tdf
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count60 IS
PORT(clk,clr,en:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END count60;
ARCHITECTURE e
www.eeworm.com/read/225193/14550859
vhd foudiv.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity foudiv is
port(
clk,pclk :in std_logic; --clk：待分频时钟 pclk：按键
clkmd:in std_logic;--按键加减模式
rst:in st
www.eeworm.com/read/225193/14550980
bak foudiv.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity foudiv is
port(
clk,pclk :in std_logic; --clk：待分频时钟 pclk：按键
clkmd:in std_logic;--按键加减模式
rst:in st
www.eeworm.com/read/224975/14558250
vhd mem_interface_top_ddr_controller_0.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
---
www.eeworm.com/read/224975/14558346
vhd mem_interface_top_ddr_controller_0.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
---
www.eeworm.com/read/224721/14570787
vhd ddr_data_path.vhd
--
-- LOGIC CORE: DDR Data Path Module
-- MODULE NAME: ddr_data_path()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- R
www.eeworm.com/read/224721/14570793
vhd ddr_sdram_tb.vhd
--/******************************************************************************
--*
--* LOGIC CORE: SDR SDRAM Controller test bench
--* MODULE NAME: sdr_sdram_tb()
--*
www.eeworm.com/read/224721/14570808
vhd ddr_data_path.vhd
--
-- LOGIC CORE: DDR Data Path Module
-- MODULE NAME: ddr_data_path()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- R
www.eeworm.com/read/124206/14589927
vhd keyboard1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY KEYBOARD1 IS
PORT (
clk