📄 sum99.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum99 is
port(k: in std_logic_vector(9 downto 0);
clk: in std_logic;
en: in std_logic;
reset: in std_logic;
out1: out std_logic_vector(9 downto 0) );
end entity sum99;
architecture art of sum99 is
signal temp: std_logic_vector(9 downto 0);
begin
process(clk, en, reset) is
begin
if reset='1' then
temp<="0000000000";
else
if clk'event and clk='1' then
if en='1' then
temp<=temp+k;
end if;
end if;
end if;
out1<=temp;
end process;
end architecture art;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -