count60.tdf

VHDL 函数信号发生器 VHDL 函数信号发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count60 IS
PORT(clk,clr,en:IN STD_LOGIC;
     q:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END count60;
ARCHITECTURE example OF  cout60 IS
SIGNAL count_60:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
q<=count_60;
PROCESS(clk,clr)
BEGIN
IF(clr='1')THEN
count_60<="000000";
ELSIF(clk'EVENT AND clk='1')THEN
IF(en='1')THEN
IF(count="111011")THEN
count_60<="000000"
ELSE
count_60<=count_60+1;
END IF;
END IF;
END IF;
END PROCESS;
END example;