foudiv.vhd.bak

可以实现对任意波形分任意频

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity foudiv is
	port(
			clk,pclk	:in std_logic; --clk：待分频时钟  pclk：按键
			clkmd:in std_logic;--按键加减模式
			rst:in std_logic;--复位,
			fout:out std_logic--频率输出
		);
end;
architecture lammy of foudiv is
	signal switch:std_logic;
	signal full:std_logic;
	signal fullup:std_logic;
	signal fulldo:std_logic;
	signal db:std_logic_vector(7 downto 0);
	signal du:std_logic_vector(7 downto 0);
	signal dd:std_logic_vector(7 downto 0);
begin
lammy01:process(pclk,rst,clkmd)
	begin
		if rst='1' then db<=(others=>'0');
		elsif pclk'event and pclk='1' then 
			if clkmd='1' then db<=db+1;
			elsif clkmd='0' then db<=db-1;
			end if;
		end if;
	end process;
lammy02:process(clk)	
	variable	updata:std_logic_vector(7 downto 0);
	begin
		if rst='1' then fullup<='0';
		elsif clk'event and clk='1' then 
			if updata=(db - 1) then updata:=(others=>'0');fullup<='1';
			elsif updata<(db - 1) then fullup<=not fullup;updata:=updata+1;
			end if;
		end if;		
		du<=updata;
	end process;
lammy03:process(clk)	
	variable	dodata:std_logic_vector(7 downto 0);
	begin
		if rst='1' then fulldo<='0';
		elsif clk'event and clk='0' then 
			if dodata=(db - 1) then dodata:=(others=>'0');fulldo<='1';
			elsif dodata<(db - 1) then fulldo<=not fulldo;dodata:=dodata+1;
			end if;
		end if;		
		dd<=dodata;
	end process;
	full<=fulldo or fullup;
lammy04:process(full)
	
	variable cnt8:std_logic_vector(7 downto 0);
		begin
--		if rst='1' then fout<='0';
		cnt8:=du+dd;
		if cnt8=db then switch<='1';
		else switch<='0';
		end if;
	end process;
lammy05:process(switch)
	variable cnt2:std_logic;
	begin
		if full'event and full='1' then cnt2:=not cnt2;
			if cnt2='1' then fout<='1'; 
			else fout<='0';
			end if;
		end if;
	end process;
end;