代码搜索:Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
www.eeworm.com/read/149607/12362864

txt state_moor_mealy.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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txt moor1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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txt moor2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
www.eeworm.com/read/149022/12409118

vhd uart.vhd

----------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This program
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vhd iu.vhd

----------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This program
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vhd ramlib.vhd

----------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This program
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vhd mctrl.vhd

----------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This program
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vhd counter32b.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter32b is port ( fin : in std_logic; clr : in std_logic; enabl : in std_logic;
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vhd l_synplify.vhd

-- Altera Microperipheral Reference Design Version 0802 ----------------------------------------------------------------------------- --
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vhd jiaotongdeng.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin1 is port(clk:in std_logic; outy1,outy4:out std_logic); end fenpin1; architecture beha of fe