ramlib.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Package: 	ramlib
-- File:	ramlib.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	
--
-- Library of ram models used for the caches and register file.
-- Various naming conventions are used to force the synthesis tools
-- to instanciate the right ram block. There should be a standard
-- for this really. Note that the three-port register file is built
-- from two identical dual-port rams, where the write-ports are
-- connected together.
------------------------------------------------------------------------------
-- Version control:
-- 06-12-1998:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

-- Simple asynchronous single-port ram model

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_arith.all;

-- pragma translate_off

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_arith.all;

entity syncram is
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    address  : in std_logic_vector((depth -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
  ); 
end syncram;     

architecture behavioral of syncram is

  subtype word is std_logic_vector((width -1) downto 0);
  type mem is array(0 to (2**depth -1)) of word;

begin

  main : process(clk)
  variable memarr : mem;
  begin
    if clk'event and clk = '1' then
      if enable = '1' then
        if not is_x(address) then
          if write = '1' then
            memarr(conv_integer(unsigned(address))) := datain;
          end if;
          dataout <= memarr(conv_integer(unsigned(address)));
        end if;
      end if;
    end if;
  end process;
 
end behavioral;

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_arith.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

-- altera dpram

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.sparcv8.all;
use work.iface.all;

entity dpram is
	port (data: in std_logic_vector (31 downto 0);
	rdaddress: in std_logic_vector (RABITS -1 downto 0);
	wraddress: in std_logic_vector (RABITS -1 downto 0);
  	rden, wren : in std_logic;
	inclock, inclocken : in std_logic;
	q: out std_logic_vector (31 downto 0));
end;

architecture behav of dpram is
begin

  rp : process(inclock, inclocken, rdaddress, rden, wren, wraddress, data, rden)
  subtype dword is std_logic_vector(31 downto 0);
  type dregtype is array (0 to IREGNUM - 1) of DWord;
  variable rfd : dregtype;
  begin
    if inclock'event and (inclock = '1') and (inclocken = '1') then
      if wren = '1' then
        if not is_x (wraddress) then 
   	  rfd(conv_integer(unsigned(wraddress))) := data; 
	end if;
      end if;
    end if;
    if rden = '1' then
      if not is_x (rdaddress) then 
        q <= rfd(conv_integer(unsigned(rdaddress)));
      end if;
    end if;
  end process;
end;

-- generic register-file

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity rfgen is
  port (
    Clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end;

architecture behav of rfgen is
begin

  rp : process(Clk, rfi)
  subtype dword is std_logic_vector(31 downto 0);
--  subtype cword is std_logic_vector(6 downto 0);
  type dregtype is array (0 to IREGNUM - 1) of DWord;
--  type cregtype is array (0 to IREGNUM - 1) of CWord;
  variable rfd : dregtype;
--  variable rfc : cregtype;
  begin
    if clk'event and (clk = '1') then
      if (holdn = '1') or GATEDCLK then
        if rfi.wren = '1' then
          if not is_x (rfi.wraddr) then 
	    rfd(conv_integer(unsigned(rfi.wraddr)) mod IREGNUM) := rfi.wrdata; 
--          rfc(conv_integer(unsigned(rfi.wraddr)) mod IREGNUM) := dpo.cb;
          end if;
        end if;
      end if;
    end if;
    if is_x (rfi.rd1addr) then 
      rfo.data1 <= (others => 'X');
    else
      rfo.data1 <= rfd(conv_integer(unsigned(rfi.rd1addr)) mod IREGNUM);
--    rfo.cb1 <= rfc(conv_integer(unsigned(rfi.rd1addr)) mod IREGNUM); 
    end if;
    if is_x (rfi.rd2addr) then 
      rfo.data2 <= (others => 'X');
    else
      rfo.data2 <= rfd(conv_integer(unsigned(rfi.rd2addr)) mod IREGNUM);
--    rfo.cb2 <= rfc(conv_integer(unsigned(rfi.rd2addr)) mod IREGNUM); 
    end if;
  end process;
end;

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;

entity syn_dpram_ruwr is
       port ( Data    : in std_logic_vector(31 downto 0);
              RdAddress : in std_logic_vector(RABITS -1  downto 0);
              WrAddress : in std_logic_vector(RABITS -1  downto 0);
              RdEn : in std_logic;
              WrEn : in std_logic;
              Q : out std_logic_vector(31 downto 0);
              WrClock : in std_logic;
              WrClken : in std_logic
           );
end;

architecture behav of syn_dpram_ruwr is

component dpram
	port (data: in std_logic_vector (31 downto 0);
	rdaddress: in std_logic_vector (RABITS -1 downto 0);
	wraddress: in std_logic_vector (RABITS -1 downto 0);
  	rden, wren : in std_logic;
	inclock, inclocken : in std_logic;
	q: out std_logic_vector (31 downto 0));
end component;

begin

  dp1 : dpram port map
    (Data, RdAddress, WrAddress, RdEn, WrEn, WrClock, WrClken, Q);
end;

-- pragma translate_on
-- regfile for altera/synopsys

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity rfaltsyno is
  port (
    clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end;

architecture rtl of rfaltsyno is

component syn_dpram_ruwr
       port ( Data    : in std_logic_vector(31 downto 0);
              RdAddress : in std_logic_vector(RABITS-1 downto 0);
              WrAddress : in std_logic_vector(RABITS-1 downto 0);
              RdEn : in std_logic;
              WrEn : in std_logic;
              Q : out std_logic_vector(31 downto 0);
              WrClock : in std_logic;
              WrClken : in std_logic
           );
end component;

signal wrclken  : std_logic;
signal rden  : std_logic;

begin

  rden <= '1';
  wrclken <= holdn when not GATEDCLK else '1';

  rfa : syn_dpram_ruwr 
    port map (
	data => rfi.wrdata, 
	rdaddress => rfi.rd1addr, 
	wraddress => rfi.wraddr,
	rden => rden, 
	wren => rfi.wren, 
	wrclock => clk, wrclken => wrclken,
	q => rfo.data1
    );

  rfb : syn_dpram_ruwr 
    port map (
	data => rfi.wrdata, 
	rdaddress => rfi.rd2addr, 
	wraddress => rfi.wraddr,
	rden => rden, 
	wren => rfi.wren, 
	wrclock => clk, wrclken => wrclken,
	q => rfo.data2
    );

end;

-- register file for altera/synplify

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity rfaltsynp is
  port (
    clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
attribute syn_isclock : boolean;
attribute syn_isclock of clk : signal is true;
end;

architecture arch0 of rfaltsynp is

component dpram
	port (data: in std_logic_vector (31 downto 0);
	rdaddress: in std_logic_vector (RABITS-1 downto 0);
	wraddress: in std_logic_vector (RABITS-1 downto 0);
  	rden, wren : in std_logic;
	inclock, inclocken : in std_logic;
	q: out std_logic_vector (31 downto 0));
end component;

-- Assign the appropriate attribute values.
attribute syn_white_box : boolean;
attribute syn_white_box of dpram : component is true;
attribute syn_scaletiming : string;
attribute syn_scaletiming of dpram : component is "eab_scale";
attribute syn_tsu1 : string;
attribute syn_tsu2 : string;
attribute syn_tsu3 : string;
attribute syn_tpd1 : string;
attribute syn_tsu1 of dpram : component is "data[*]->inclock=5.3";
attribute syn_tsu2 of dpram : component is "wraddress[*]->inclock=5.3";
attribute syn_tsu3 of dpram : component is "wren->inclock=5.5";
attribute syn_tpd1 of dpram : component is "rdaddress[*]->q[*]=13.7";
attribute WIDTH : positive;
attribute WIDTH of dpram: component is 32;
attribute WIDTHAD : positive;
attribute WIDTHAD of dpram: component is 8; 
attribute WRADDRESS_REG : string;
attribute WRADDRESS_REG of dpram: component is "INCLOCK"; 
attribute WRCONTROL_REG : string;
attribute WRCONTROL_REG of dpram: component is "INCLOCK"; 
attribute INDATA_REG : string;
attribute INDATA_REG of dpram: component is "INCLOCK"; 
attribute RDADDRESS_REG : string;
attribute RDADDRESS_REG of dpram: component is "UNREGISTERED"; 
attribute RDCONTROL_REG : string;
attribute RDCONTROL_REG of dpram: component is "UNREGISTERED"; 
attribute OUTDATA_REG : string;
attribute OUTDATA_REG of dpram: component is "UNREGISTERED"; 
attribute WRADDRESS_ACLR : string;
attribute WRADDRESS_ACLR of dpram: component is "OFF"; 
attribute WRCONTROL_ACLR : string;
attribute WRCONTROL_ACLR of dpram: component is "OFF"; 
attribute RDADDRESS_ACLR : string;
attribute RDADDRESS_ACLR of dpram: component is "OFF"; 
attribute RDCONTROL_ACLR : string;
attribute RDCONTROL_ACLR of dpram: component is "OFF"; 
attribute LPM_TYPE : string;
attribute LPM_TYPE of dpram: component is "ALTDPRAM";

signal vcc, wrclken : std_logic;

begin
  vcc <= '1';
  wrclken <= holdn when not GATEDCLK else '1';

  u1: dpram  port map (rfi.wrdata, rfi.rd1addr, rfi.wraddr, vcc, 
			rfi.wren, clk, wrclken, rfo.data1);
  u2: dpram  port map (rfi.wrdata, rfi.rd2addr, rfi.wraddr, vcc, 
			rfi.wren, clk, wrclken, rfo.data2);

end arch0;

-- dpram for leonardo

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity dpramleo is
  port (
    data: in std_logic_vector (31 downto 0);
    rdaddress: in std_logic_vector (RABITS -1 downto 0);
    wraddress: in std_logic_vector (RABITS -1 downto 0);
    wren : in std_logic;
    clock : in std_logic;
    q: out std_logic_vector (31 downto 0));
end;

architecture behav of dpramleo is
  subtype dword is std_logic_vector(31 downto 0);
  type dregtype is array (0 to IREGNUM - 1) of DWord;
  signal rfd : dregtype;
begin

  rp : process(clock, rdaddress, rfd)
  begin
    if clock'event and (clock = '1') then
      if wren = '1' then
   	  rfd(conv_integer(unsigned(wraddress))) <= data; 
      end if;
    end if;
    q <= rfd(conv_integer(unsigned(rdaddress)));
  end process;
end;

-- register file for leonardo

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity rfaltleo is
  port (
    clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end;

architecture arch0 of rfaltleo is

component dpramleo
  port (
    data: in std_logic_vector (31 downto 0);
    rdaddress: in std_logic_vector (RABITS -1 downto 0);
    wraddress: in std_logic_vector (RABITS -1 downto 0);
    wren : in std_logic;
    clock : in std_logic;
    q: out std_logic_vector (31 downto 0));
end component;

  subtype dword is std_logic_vector(31 downto 0);
  type dregtype is array (0 to IREGNUM - 1) of DWord;

  signal  wren : std_logic;
  signal rfd : dregtype;

begin

  wren <= holdn and rfi.wren;

  u1: dpramleo  port map (rfi.wrdata, rfi.rd1addr, rfi.wraddr, 
			wren, clk, rfo.data1);
  u2: dpramleo  port map (rfi.wrdata, rfi.rd2addr, rfi.wraddr, 
			wren, clk, rfo.data2);

end arch0;

-- synchronous ram for leonardo

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_arith.all;

entity syncramleo is
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    address  : in std_logic_vector((depth -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
  ); 
end syncramleo;     

architecture behavioral of syncramleo is

  subtype word is std_logic_vector((width -1) downto 0);
  type mem is array(0 to (2**depth -1)) of word;
  signal memarr : mem;
  signal ra  : std_logic_vector((depth -1) downto 0);

begin

  main : process(clk, memarr, ra)
  begin
    if clk'event and clk = '1' then