jiaotongdeng.vhd

这是一个用硬件描述语言来设计的交通灯程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin1 is
  port(clk:in std_logic;
        outy1,outy4:out std_logic);
  end fenpin1;
architecture beha of fenpin1 is
   signal c1:std_logic_vector(2 downto 0);
   signal c2,c4:std_logic;
   signal c3:std_logic_vector(2 downto 0);
begin
  process(clk)
   begin
    if(clk'event and clk='0')then
     c1<=c1+1;
     if c1="100" then
      c2<=not c2;
       c1<="000";
     end if;
    end if;
  end process;
 process(c2)
   begin
    if c2'event and c2='0' then
       c3<=c3+1;
    if c3="011" then
       c4<=not c4;
       c3<="000";
    end if;
    end if;
end process;
outy1<=c2;
outy4<=c4;
end beha;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity moore_jt2 is
   port(clk,din: in std_logic;
        en0,en1: out std_Logic;
        dataout :out std_logic_vector(5 downto 0));
end moore_jt2;
 architecture one of moore_jt2 is
   type state_type is(s1,s2,s3,s4,s5);
signal state:state_type;
 begin
 process(clk)
 begin
    if clk'event and clk='1' then
      case state is
         when s1=>if din='1' then state<=s2;
                  end if;
         when s2=>if din='1' then state<=s3;
                else state<=s1;
                 end if;
         when s3=>if din='1' then state<=s4;
                   else state<=s2;
                   end if;
         when s4=>if din='1' then  state<=s5;
                      else state<=s3;
                  end if;
         when s5=>if din='0' then
                 state<=s4;
                 end if;
         when others=>state<=s1;
         end case;
   end if;
   end process;
 process(state)
   begin
    case state is
       when s1=>dataout<="011110";
       when s2=>dataout<="011101";
       when s3=>dataout<="101101";
       when s4=>dataout<="101011";
       when s5=>dataout<="110011";
     end case;
end process;
  en0<='1';
  en1<='1';
end one;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jiaotongdeng is
  port(clk:in std_logic;
        en0: out std_logic;
        en1:out std_logic;
        output: out std_logic_vector(5 downto 0));
end jiaotongdeng;
architecture art of jiaotongdeng is

 component fenpin1 
  port(clk:in std_logic;
        outy1,outy4:out std_logic);
  end   component;
 component moore_jt2 
   port(clk,din: in std_logic;
        en0,en1: out std_Logic;
        dataout :out std_logic_vector(5 downto 0));
end component;
  signal x ,y :std_logic;
   begin
  u1: fenpin1 port map (clk,x,y); 
  u2: moore_jt2 port map(x,not y,en0,en1,output);
end architecture art;