counter32b.vhd

用VHDL语言设计的频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter32b is
   port ( fin : in std_logic;
          clr : in std_logic;
        enabl : in std_logic;
        dout  : out std_logic_vector ( 31 downto 0 ) );
end entity counter32b ;

architecture behave_counter32b of counter32b is 
   signal cqi : std_logic_vector ( 31 downto 0 );
   signal conv : std_logic_vector ( 31 downto 0 );
   begin
  p1: process ( fin ,clr,enabl )
    begin
      if clr='1' then cqi <= (others =>'0');
        elsif fin'event and fin='1' then
          if enabl = '1' then
 if cqi ( 3 downto 0 )<9 then
                  cqi <= cqi+1;
               else cqi ( 3 downto 0 ) <="0000";
                  if cqi ( 7 downto 4 ) < 9 then
                     cqi ( 7 downto 4 ) <= cqi( 7 downto 4 )+1;
                  else cqi ( 7 downto 4 ) <= "0000";
                     if cqi ( 11 downto 8 ) < 9 then 
                        cqi ( 11 downto 8 ) <= cqi ( 11 downto 8 ) +1;
                      else cqi ( 11 downto 8 ) <= "0000";
                        if cqi ( 15 downto 12 ) < 9 then 
                           cqi ( 15 downto 12 ) <= cqi ( 15 downto 12 ) +1;
                        else cqi ( 15 downto 12 ) <= "0000";
                           if cqi ( 19 downto 16 ) < 9 then 
                              cqi ( 19 downto 16 ) <= cqi ( 19 downto 16) +1;
                           else cqi ( 19 downto 16 ) <= "0000";
                              if cqi ( 23 downto 20 ) < 9 then 
                                 cqi ( 23 downto 20 ) <= cqi ( 23 downto 20 ) +1;
                              else cqi ( 23 downto 20 ) <= "0000";
                                if cqi ( 27 downto 24 ) < 9 then 
                                   cqi ( 27 downto 24 ) <= cqi ( 27 downto 24 ) +1;
                                else cqi ( 27 downto 24 ) <= "0000";
                                   if cqi ( 31 downto 28 ) < 9 then 
                                      cqi ( 31 downto 28 ) <= cqi ( 31 downto 28 ) +1;
                                   else cqi ( 31 downto 28 ) <= "0000";
                                   end if;
                                 end if;
                               end if;
                              end if;
                             end if;
                         end if;  
                   end if;
                end if;
          end if;
        end if;
 end process ;
      dout <= cqi;                  
end behave_counter32b;