代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/149929/12331574
vhd ex10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY EX10 IS
PORT(
CLK : IN STD_LOGIC;
S,M,H : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END EX10;
ARCHITEC
www.eeworm.com/read/149929/12331978
vhd moore1.vhd
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/149929/12332200
vhd moore2.vhd
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/149929/12332852
vhd cntm60v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm60v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/149929/12333004
vhd cntm100v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm100v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/149929/12333037
vhd cntm24v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm24v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in s
www.eeworm.com/read/149929/12333197
vhd cntm60v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm60v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/251490/12341274
vhd qiangdaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangdaqi is
port(k,s1,s2,s3,s4,s5,s6,s7:in std_logic;
led7s:out std_logic_vector(6 downto 0)
www.eeworm.com/read/337678/12350154
vhd compare_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare_4 is
port(a,b:in std_logic_vector(3 downto 0);
gt,eq,lt:out std_logic);
end compare_4;
architect
www.eeworm.com/read/149607/12362860
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in