qiangdaqi.vhd

用VHDL设计的7人的抢答器,优点是代码简单,特别适合初学着作为练习和增强代码编写能力的练习,好处

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangdaqi is
       port(k,s1,s2,s3,s4,s5,s6,s7:in std_logic;
            led7s:out std_logic_vector(6 downto 0));
end qiangdaqi;
ARCHITECTURE one of qiangdaqi is
       signal ENA:std_logic;
       signal q:std_logic_vector(7 downto 1);
begin
   ENA<=not(q(7)or q(6)or q(5)or q(4)or q(3)or q(2)or q(1));
   A_PRO:process(k,ENA)
      begin
        if k='0' then q<="0000000";
         elsif ena='1' and s1='1' then q<="0000001";
          elsif ena='1' and s2='1' then q<="0000010";
            elsif ena='1' and s3='1' then q<="0000100";
               elsif ena='1' and s4='1' then q<="0001000";
                  elsif ena='1' and s5='1' then q<="0010000";
                     elsif ena='1' and s6='1' then q<="0100000";
                        elsif ena='1' and s7='1' then q<="1000000";
    end if;
case q is
           when "0000000"=>led7s<="1111110";
           when "0000001"=>led7s<="0110000";
           when "0000010"=>led7s<="1101101";
           when "0000100"=>led7s<="1111001";
           when "0001000"=>led7s<="0110011";
           when "0010000"=>led7s<="1011011";
           when "0100000"=>led7s<="0011111";
           when "1000000"=>led7s<="1110000";
           when others =>led7s<="1111110";
        end case;
     end process a_pro;
end one;