ex10.vhd

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY EX10 IS
		PORT(
		CLK		: IN	STD_LOGIC;
	    S,M,H	    : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END EX10;
ARCHITECTURE a OF EX10 IS
	SIGNAL TEMP,MIN,HOUR : STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
	 PROCESS (CLK)
      BEGIN
        IF CLK'EVENT AND CLK='1' THEN
           IF TEMP=59 THEN
              TEMP<="000000";
              IF MIN=59 THEN 
                MIN<="000000";
                IF  HOUR=11 THEN
                  HOUR<="000000";
                  ELSE  HOUR<=HOUR+1;
                 END IF;
              ELSE MIN<=MIN+1; 
              END IF;
           ELSE   TEMP<=TEMP+1;
                
           END IF;
        END IF;
        S<=TEMP;
        M<=MIN;
        H<=HOUR;
    END PROCESS;

	END a;