compare_4.vhd

来自「4位比较器」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity compare_4 is
	port(a,b:in std_logic_vector(3 downto 0);
	gt,eq,lt:out std_logic);
end compare_4;

architecture compare of compare_4 is
	begin
	process(a,b)
		begin
			if(a>b) then gt<='1';
			else gt<='0';
			end if;
			if(a=b) then eq<='1';
			else eq<='0';
			end if;
			if(a<b) then lt<='1';
			else lt<='0';
			end if;
	end process;
end compare;