代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/478303/6714550
vhd ex_6_4_2_mult8_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb1 is end tb1;
architecture a of tb1
www.eeworm.com/read/478461/6717864
vhd prbsgen.vhd
prbs[1]-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
www.eeworm.com/read/478253/6722762
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/478253/6722763
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/478253/6722826
vhd mul3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
www.eeworm.com/read/478253/6722849
vhd txmit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic
www.eeworm.com/read/478253/6722850
vhd rxcver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port
www.eeworm.com/read/477908/6725576
vhd xs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity XS is
port(clk:in std_logic;
a1,a0: in std_logic_vector(3 downto 0);
sc:out std_logic);
end XS;
www.eeworm.com/read/476967/6743547
vhd hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(reset,clk:in std_logic;
daout:out std_logic_vector(7 downto 0));
end hour;
architecture behave o
www.eeworm.com/read/476967/6743595
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port(reset,clk,setmin:in std_logic;
enmin:out std_logic;
daout:out std_logic_vector(7 downto 0));