prbsgen.vhd

Clock data recovery .........good example

prbs[1]-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: prbs_gen.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is a PRBS generator 
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity prbsgen is
    Port (      CLK		: in	STD_LOGIC; 
		EN		: in    std_logic;
		RST		: in	STD_LOGIC;
		PRBSOUT		: out	std_logic);
end prbsgen;

architecture Behavioral of prbsgen is

SIGNAL 
	x	: STD_LOGIC_VECTOR(31 downto 0);

begin

PRBSOUT <= x(0);

PROCESS(CLK,RST)
begin
if RST='0' then
		x <=x"55555555";
elsif CLK='1' and CLK'event and EN='1' then
		x(0) <= x(31) XOR x(28);
		x(31 downto 1) <= x(30 downto 0);		
end if;
end PROCESS;


end Behavioral;