xs.vhd

来自「基于fpga数字钟系统」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity XS is
 port(clk:in std_logic;
      a1,a0: in std_logic_vector(3 downto 0);
      sc:out std_logic);
end XS;
architecture m of XS is
begin 
process(a0,a1)
--variable x:std_logic_vector(5 downto 0);
variable y:std_logic;
begin
  if a1="0101" and a0 >"0111" then
     --if clk'event and clk='1' then
      --  if x="111011" then
          -- x:="000000";
           --y:='0';
        --else
           -- x:=x+'1';
            --y:='1';
        -- end if;
    --end if;
       y:=clk;
  end if;
     sc<=y;
end process;
end m;