hour.vhd

来自「有关数字钟的」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(reset,clk:in std_logic;
	daout:out std_logic_vector(7 downto 0));
end hour;
architecture behave of hour is
begin
process(reset,clk)
variable da1:std_logic_vector(3 downto 0);
variable da2:std_logic_vector(3 downto 0);
begin
if(reset='0') then da1:="0000";da2:="0000";
else
	if(clk'event and clk='1') then da1:=da1+1;
		if(da1>"1001") then da2:=da2+1;da1:="0000";
		end if;
		if(da2>="0010"and da1>="0100")then da2:="0000";da1:="0000";
		end if;
	end if;
end if;
daout(7 downto 4)<=da2;
daout(3 downto 0)<=da1;
end process;
end behave;