代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/484140/6591327
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/481905/6632165
vhd sinc_v.vhd
----------------------------------------------------------------------------------
-- Bufon, Ferluga
-- Progetto elettronica 2 FPGA
-- Termometro visualizzato su VGA
------------------------------
www.eeworm.com/read/481905/6632196
vhd sinc_h.vhd
----------------------------------------------------------------------------------
-- Bufon, Ferluga
-- Progetto elettronica 2 FPGA
-- Termometro visualizzato su VGA
----------------------------------
www.eeworm.com/read/481905/6632341
vhd contatore.vhd
-- Required Libraries
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- 4-bit synchronous counter with count enable,
--
www.eeworm.com/read/481905/6632357
vhd contatore.vhd
-- Required Libraries
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- 4-bit synchronous counter with count enable,
--
www.eeworm.com/read/480656/6659595
txt 新建文本文档.txt
一﹑指标要求：. A: f5 b; G% A( d8 n
（１）设计一个4位十进制的频率计其测量范围1Hz~9.999KHz；6 N3 G8 k( U- @' n* A
（２）记数过程结束后，保存并显示结果；
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/480670/6659739
txt 新建文本文档(2).txt
一﹑指标要求：. A: f5 b; G% A( d8 n
（１）设计一个4位十进制的频率计其测量范围1Hz~9.999KHz；6 N3 G8 k( U- @' n* A
（２）记数过程结束后，保存并显示结果；
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/479733/6685531
vhd sysctrl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY sysctrl IS
PORT( clk1 : IN STD_LOGIC;
clk2 : IN STD_LOGIC;
clk3 : IN STD_LOGIC;
clk4 : IN STD_LOGIC;
www.eeworm.com/read/478303/6714476
vhd ex_p3_17_divider.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity DIVIDER is
port(A,B : in STD_LOGIC_VECTOR(7 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0);
ST_A,S
www.eeworm.com/read/478303/6714480
vhd ex_3_9_2_mult8_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb1 is end tb1;
architecture a of tb1