contatore.vhd

来自「simple thermometr in vhdl」· VHDL 代码 · 共 57 行

 
-- Required Libraries 
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
 
-- 4-bit synchronous counter with count enable, 
-- asynchronous reset and synchronous load
--     CLK: in STD_LOGIC;
--     RESET: in STD_LOGIC;
--     CE, LOAD, DIR: in STD_LOGIC;
--     DIN: in STD_LOGIC_VECTOR(3 downto 0);
--     COUNT: inout STD_LOGIC_VECTOR(3 downto 0);
 

 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kontator is
port(
CLK: in STD_LOGIC;
COUNT: inout STD_LOGIC_VECTOR(28 downto 0));
end kontator;

architecture Behavioral of kontator is

begin
 process (CLK) 
begin
  -- if RESET='1' then 
 --     COUNT <= "0000";
   if CLK='1' and CLK'event then
  --    if CE='1' then
  --       if LOAD='1' then
   --   	   COUNT <= DIN;
    --     else 
     --       if DIR='1' then  
               COUNT <= COUNT + 1;
      --      else
      --         COUNT <= COUNT - 1;
        --    end if;
       --  end if;
     -- end if;
   end if;
end process;

end Behavioral;