代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/490611/6449683

vhd bbusmultiplexer.vhd

--**************************************************************************************************** -- B bus multiplexer for ARM7TDMI-S processor -- Designed by Ruslan Lepetenok -- Modified 04.1
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vhd datamux.vhd

--**************************************************************************************************** -- Data multiplexer for ARM memory sybsistem -- Designed by Ruslan Lepetenok -- Modified 07.12
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www.eeworm.com/read/489800/6461488

vhd counter6.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter6 IS PORT(clk,clr:IN STD_LOGIC; oc:OUT STD_LOGIC; y0,y1:OUT STD_LOGIC_VECTOR(3 DOWNTO
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vhd plj.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen is port(clk:in std_logic; q:out std_logic); end fen; architecture rtl of fen is signal cq:std_log
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bak plj.vhd.bak

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen is port(clk:in std_logic; q:out std_logic); end fen; architecture rtl of fen is signal cq:std_log
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bak vga_controller.vhd.bak

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity VGA_Controller is port ( --VGA Side BLANK : out std_logic; SYNC : out std_logic; VGA_CLK : out std_
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vhd vga_controller.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity VGA_Controller is port ( --VGA Side BLANK : out std_logic; SYNC : out std_logic; VGA_CLK : out std_
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www.eeworm.com/read/487908/6501824

txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/487908/6501848

txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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